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[X86] Add the VR128L/H and VR256L/H to the list of vector register classes for inline asm constraints. Also fix the comment on the function.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271802 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2016-06-04 20:15:08 +00:00
parent 101b01e9b3
commit c21f33738d
1 changed files with 5 additions and 1 deletions
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6
lib/Target/X86/X86ISelLowering.cpp
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@ -30693,7 +30693,7 @@ static bool isGRClass(const TargetRegisterClass &RC) {
}
}
/// Check if \p RC is a general purpose register class.
/// Check if \p RC is a vector register class.
/// I.e., FR* / VR* or one of their variant.
static bool isFRClass(const TargetRegisterClass &RC) {
switch (RC.getID()) {
@ -30704,8 +30704,12 @@ static bool isFRClass(const TargetRegisterClass &RC) {
case X86::FR128RegClassID:
case X86::VR64RegClassID:
case X86::VR128RegClassID:
case X86::VR128LRegClassID:
case X86::VR128HRegClassID:
case X86::VR128XRegClassID:
case X86::VR256RegClassID:
case X86::VR256LRegClassID:
case X86::VR256HRegClassID:
case X86::VR256XRegClassID:
case X86::VR512RegClassID:
return true;