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Teach dwarf writer to handle complex address expression for .debug_loc entries.
This fixes clang generated blocks' variables' debug info. Radar 9279956. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130373 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -379,6 +379,10 @@ namespace llvm {
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/// operands.
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virtual MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
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/// getDwarfRegOpSize - get size required to emit given machine location
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/// using dwarf encoding.
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virtual unsigned getDwarfRegOpSize(const MachineLocation &MLoc) const;
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/// getISAEncoding - Get the value for DW_AT_APPLE_isa. Zero if no isa
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/// encoding specified.
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virtual unsigned getISAEncoding() { return 0; }
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@ -749,33 +749,49 @@ getDebugValueLocation(const MachineInstr *MI) const {
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return MachineLocation();
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}
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/// getDwarfRegOpSize - get size required to emit given machine location using
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/// dwarf encoding.
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unsigned AsmPrinter::getDwarfRegOpSize(const MachineLocation &MLoc) const {
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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unsigned DWReg = RI->getDwarfRegNum(MLoc.getReg(), false);
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if (int Offset = MLoc.getOffset()) {
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// If the value is at a certain offset from frame register then
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// use DW_OP_breg.
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if (DWReg < 32)
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return 1 + MCAsmInfo::getSLEB128Size(Offset);
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else
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return 1 + MCAsmInfo::getULEB128Size(MLoc.getReg())
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+ MCAsmInfo::getSLEB128Size(Offset);
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}
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if (DWReg < 32)
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return 1;
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return 1 + MCAsmInfo::getULEB128Size(DWReg);
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}
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/// EmitDwarfRegOp - Emit dwarf register operation.
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void AsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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unsigned Reg = RI->getDwarfRegNum(MLoc.getReg(), false);
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const TargetRegisterInfo *TRI = TM.getRegisterInfo();
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unsigned Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
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if (int Offset = MLoc.getOffset()) {
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// If the value is at a certain offset from frame register then
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// use DW_OP_fbreg.
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unsigned OffsetSize = Offset ? MCAsmInfo::getSLEB128Size(Offset) : 1;
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OutStreamer.AddComment("Loc expr size");
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EmitInt16(1 + OffsetSize);
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OutStreamer.AddComment(
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dwarf::OperationEncodingString(dwarf::DW_OP_fbreg));
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EmitInt8(dwarf::DW_OP_fbreg);
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OutStreamer.AddComment("Offset");
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if (Reg < 32) {
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OutStreamer.AddComment(
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dwarf::OperationEncodingString(dwarf::DW_OP_breg0 + Reg));
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EmitInt8(dwarf::DW_OP_breg0 + Reg);
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} else {
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OutStreamer.AddComment("DW_OP_bregx");
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EmitInt8(dwarf::DW_OP_bregx);
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OutStreamer.AddComment(Twine(Reg));
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EmitULEB128(Reg);
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}
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EmitSLEB128(Offset);
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} else {
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if (Reg < 32) {
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OutStreamer.AddComment("Loc expr size");
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EmitInt16(1);
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OutStreamer.AddComment(
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dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg));
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EmitInt8(dwarf::DW_OP_reg0 + Reg);
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} else {
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OutStreamer.AddComment("Loc expr size");
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EmitInt16(1 + MCAsmInfo::getULEB128Size(Reg));
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OutStreamer.AddComment(
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dwarf::OperationEncodingString(dwarf::DW_OP_regx));
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OutStreamer.AddComment("DW_OP_regx");
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EmitInt8(dwarf::DW_OP_regx);
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OutStreamer.AddComment(Twine(Reg));
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EmitULEB128(Reg);
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@ -258,15 +258,22 @@ void CompileUnit::addComplexAddress(DbgVariable *&DV, DIE *Die,
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unsigned Attribute,
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const MachineLocation &Location) {
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DIEBlock *Block = new (DIEValueAllocator) DIEBlock();
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if (Location.isReg())
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addRegisterOp(Block, Location.getReg());
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unsigned N = DV->getNumAddrElements();
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unsigned i = 0;
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if (Location.isReg()) {
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if (N >= 2 && DV->getAddrElement(0) == DIBuilder::OpPlus) {
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// If first address element is OpPlus then emit
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// DW_OP_breg + Offset instead of DW_OP_reg + Offset.
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addRegisterOffset(Block, Location.getReg(), DV->getAddrElement(1));
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i = 2;
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} else
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addRegisterOp(Block, Location.getReg());
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}
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else
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addRegisterOffset(Block, Location.getReg(), Location.getOffset());
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for (unsigned i = 0, N = DV->getNumAddrElements(); i < N; ++i) {
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for (;i < N; ++i) {
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uint64_t Element = DV->getAddrElement(i);
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if (Element == DIBuilder::OpPlus) {
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addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_plus_uconst);
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addUInt(Block, 0, dwarf::DW_FORM_udata, DV->getAddrElement(++i));
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@ -1466,7 +1466,7 @@ DwarfDebug::collectVariableInfo(const MachineFunction *MF,
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}
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// The value is valid until the next DBG_VALUE or clobber.
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DotDebugLocEntries.push_back(DotDebugLocEntry(FLabel, SLabel, MLoc));
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DotDebugLocEntries.push_back(DotDebugLocEntry(FLabel, SLabel, MLoc, Var));
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}
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DotDebugLocEntries.push_back(DotDebugLocEntry());
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}
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@ -2721,7 +2721,39 @@ void DwarfDebug::emitDebugLoc() {
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} else {
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Asm->OutStreamer.EmitSymbolValue(Entry.Begin, Size, 0);
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Asm->OutStreamer.EmitSymbolValue(Entry.End, Size, 0);
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Asm->EmitDwarfRegOp(Entry.Loc);
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DIVariable DV(Entry.Variable);
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if (DV.hasComplexAddress()) {
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unsigned N = DV.getNumAddrElements();
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unsigned i = 0;
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Asm->OutStreamer.AddComment("Loc expr size");
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if (N >= 2 && DV.getAddrElement(0) == DIBuilder::OpPlus) {
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// If first address element is OpPlus then emit
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// DW_OP_breg + Offset instead of DW_OP_reg + Offset.
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MachineLocation Loc(Entry.Loc.getReg(), DV.getAddrElement(1));
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Asm->EmitInt16(Asm->getDwarfRegOpSize(Loc) + N - 2);
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Asm->EmitDwarfRegOp(Loc);
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// Asm->EmitULEB128(DV.getAddrElement(1));
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i = 2;
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} else {
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Asm->EmitInt16(Asm->getDwarfRegOpSize(Entry.Loc) + N);
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Asm->EmitDwarfRegOp(Entry.Loc);
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}
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// Emit remaining complex address elements.
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for (; i < N; ++i) {
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uint64_t Element = DV.getAddrElement(i);
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if (Element == DIBuilder::OpPlus) {
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Asm->EmitInt8(dwarf::DW_OP_plus_uconst);
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Asm->EmitULEB128(DV.getAddrElement(++i));
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} else if (Element == DIBuilder::OpDeref)
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Asm->EmitInt8(dwarf::DW_OP_deref);
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else llvm_unreachable("unknown Opcode found in complex address");
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}
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} else {
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Asm->OutStreamer.AddComment("Loc expr size");
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Asm->EmitInt16(Asm->getDwarfRegOpSize(Entry.Loc));
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Asm->EmitDwarfRegOp(Entry.Loc);
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}
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}
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}
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}
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@ -66,10 +66,12 @@ typedef struct DotDebugLocEntry {
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const MCSymbol *Begin;
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const MCSymbol *End;
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MachineLocation Loc;
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const MDNode *Variable;
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bool Merged;
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DotDebugLocEntry() : Begin(0), End(0), Merged(false) {}
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DotDebugLocEntry(const MCSymbol *B, const MCSymbol *E, MachineLocation &L)
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: Begin(B), End(E), Loc(L), Merged(false) {}
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DotDebugLocEntry() : Begin(0), End(0), Variable(0), Merged(false) {}
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DotDebugLocEntry(const MCSymbol *B, const MCSymbol *E, MachineLocation &L,
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const MDNode *V)
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: Begin(B), End(E), Loc(L), Variable(V), Merged(false) {}
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/// Empty entries are also used as a trigger to emit temp label. Such
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/// labels are referenced is used to find debug_loc offset for a given DIE.
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bool isEmpty() { return Begin == 0 && End == 0; }
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@ -172,6 +172,47 @@ getDebugValueLocation(const MachineInstr *MI) const {
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return Location;
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}
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/// getDwarfRegOpSize - get size required to emit given machine location using
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/// dwarf encoding.
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unsigned ARMAsmPrinter::getDwarfRegOpSize(const MachineLocation &MLoc) const {
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
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return AsmPrinter::getDwarfRegOpSize(MLoc);
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else {
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unsigned Reg = MLoc.getReg();
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if (Reg >= ARM::S0 && Reg <= ARM::S31) {
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assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
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// S registers are described as bit-pieces of a register
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// S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
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// S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
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unsigned SReg = Reg - ARM::S0;
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unsigned Rx = 256 + (SReg >> 1);
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OutStreamer.AddComment("Loc expr size");
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// DW_OP_regx + ULEB + DW_OP_bit_piece + ULEB + ULEB
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// 1 + ULEB(Rx) + 1 + 1 + 1
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return 4 + MCAsmInfo::getULEB128Size(Rx);
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}
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if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
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assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
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// Q registers Q0-Q15 are described by composing two D registers together.
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// Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1) DW_OP_piece(8)
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unsigned QReg = Reg - ARM::Q0;
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unsigned D1 = 256 + 2 * QReg;
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unsigned D2 = D1 + 1;
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OutStreamer.AddComment("Loc expr size");
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// DW_OP_regx + ULEB + DW_OP_piece + ULEB(8) +
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// DW_OP_regx + ULEB + DW_OP_piece + ULEB(8);
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// 6 + ULEB(D1) + ULEB(D2)
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return 6 + MCAsmInfo::getULEB128Size(D1) + MCAsmInfo::getULEB128Size(D2);
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}
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}
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return 0;
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}
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/// EmitDwarfRegOp - Emit dwarf register operation.
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void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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@ -89,6 +89,10 @@ public:
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MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
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/// getDwarfRegOpSize - get size required to emit given machine location
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/// using dwarf encoding.
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virtual unsigned getDwarfRegOpSize(const MachineLocation &MLoc) const;
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/// EmitDwarfRegOp - Emit dwarf register operation.
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virtual void EmitDwarfRegOp(const MachineLocation &MLoc) const;
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@ -1,5 +1,5 @@
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; RUN: llc -O0 -mtriple=arm-apple-darwin < %s | grep DW_OP_fbreg
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; Use DW_OP_fbreg in variable's location expression if the variable is in a stack slot.
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; RUN: llc -O0 -mtriple=arm-apple-darwin < %s | grep DW_OP_breg
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; Use DW_OP_breg in variable's location expression if the variable is in a stack slot.
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%struct.SVal = type { i8*, i32 }
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@ -1,5 +1,5 @@
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; RUN: llc -O0 -mtriple=x86_64-apple-darwin < %s | grep DW_OP_fbreg
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; Use DW_OP_fbreg in variable's location expression if the variable is in a stack slot.
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; RUN: llc -O0 -mtriple=x86_64-apple-darwin < %s | grep DW_OP_breg7
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; Use DW_OP_breg7 in variable's location expression if the variable is in a stack slot.
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%struct.SVal = type { i8*, i32 }
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