Teach dwarf writer to handle complex address expression for .debug_loc entries.

This fixes clang generated blocks' variables' debug info.
Radar 9279956.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130373 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Devang Patel 2011-04-28 02:22:40 +00:00
parent 450ed1a05b
commit c26f5447e3
9 changed files with 137 additions and 31 deletions

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@ -379,6 +379,10 @@ namespace llvm {
/// operands.
virtual MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
/// getDwarfRegOpSize - get size required to emit given machine location
/// using dwarf encoding.
virtual unsigned getDwarfRegOpSize(const MachineLocation &MLoc) const;
/// getISAEncoding - Get the value for DW_AT_APPLE_isa. Zero if no isa
/// encoding specified.
virtual unsigned getISAEncoding() { return 0; }

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@ -749,33 +749,49 @@ getDebugValueLocation(const MachineInstr *MI) const {
return MachineLocation();
}
/// getDwarfRegOpSize - get size required to emit given machine location using
/// dwarf encoding.
unsigned AsmPrinter::getDwarfRegOpSize(const MachineLocation &MLoc) const {
const TargetRegisterInfo *RI = TM.getRegisterInfo();
unsigned DWReg = RI->getDwarfRegNum(MLoc.getReg(), false);
if (int Offset = MLoc.getOffset()) {
// If the value is at a certain offset from frame register then
// use DW_OP_breg.
if (DWReg < 32)
return 1 + MCAsmInfo::getSLEB128Size(Offset);
else
return 1 + MCAsmInfo::getULEB128Size(MLoc.getReg())
+ MCAsmInfo::getSLEB128Size(Offset);
}
if (DWReg < 32)
return 1;
return 1 + MCAsmInfo::getULEB128Size(DWReg);
}
/// EmitDwarfRegOp - Emit dwarf register operation.
void AsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
const TargetRegisterInfo *RI = TM.getRegisterInfo();
unsigned Reg = RI->getDwarfRegNum(MLoc.getReg(), false);
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
unsigned Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
if (int Offset = MLoc.getOffset()) {
// If the value is at a certain offset from frame register then
// use DW_OP_fbreg.
unsigned OffsetSize = Offset ? MCAsmInfo::getSLEB128Size(Offset) : 1;
OutStreamer.AddComment("Loc expr size");
EmitInt16(1 + OffsetSize);
OutStreamer.AddComment(
dwarf::OperationEncodingString(dwarf::DW_OP_fbreg));
EmitInt8(dwarf::DW_OP_fbreg);
OutStreamer.AddComment("Offset");
if (Reg < 32) {
OutStreamer.AddComment(
dwarf::OperationEncodingString(dwarf::DW_OP_breg0 + Reg));
EmitInt8(dwarf::DW_OP_breg0 + Reg);
} else {
OutStreamer.AddComment("DW_OP_bregx");
EmitInt8(dwarf::DW_OP_bregx);
OutStreamer.AddComment(Twine(Reg));
EmitULEB128(Reg);
}
EmitSLEB128(Offset);
} else {
if (Reg < 32) {
OutStreamer.AddComment("Loc expr size");
EmitInt16(1);
OutStreamer.AddComment(
dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg));
EmitInt8(dwarf::DW_OP_reg0 + Reg);
} else {
OutStreamer.AddComment("Loc expr size");
EmitInt16(1 + MCAsmInfo::getULEB128Size(Reg));
OutStreamer.AddComment(
dwarf::OperationEncodingString(dwarf::DW_OP_regx));
OutStreamer.AddComment("DW_OP_regx");
EmitInt8(dwarf::DW_OP_regx);
OutStreamer.AddComment(Twine(Reg));
EmitULEB128(Reg);

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@ -258,15 +258,22 @@ void CompileUnit::addComplexAddress(DbgVariable *&DV, DIE *Die,
unsigned Attribute,
const MachineLocation &Location) {
DIEBlock *Block = new (DIEValueAllocator) DIEBlock();
if (Location.isReg())
addRegisterOp(Block, Location.getReg());
unsigned N = DV->getNumAddrElements();
unsigned i = 0;
if (Location.isReg()) {
if (N >= 2 && DV->getAddrElement(0) == DIBuilder::OpPlus) {
// If first address element is OpPlus then emit
// DW_OP_breg + Offset instead of DW_OP_reg + Offset.
addRegisterOffset(Block, Location.getReg(), DV->getAddrElement(1));
i = 2;
} else
addRegisterOp(Block, Location.getReg());
}
else
addRegisterOffset(Block, Location.getReg(), Location.getOffset());
for (unsigned i = 0, N = DV->getNumAddrElements(); i < N; ++i) {
for (;i < N; ++i) {
uint64_t Element = DV->getAddrElement(i);
if (Element == DIBuilder::OpPlus) {
addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_plus_uconst);
addUInt(Block, 0, dwarf::DW_FORM_udata, DV->getAddrElement(++i));

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@ -1466,7 +1466,7 @@ DwarfDebug::collectVariableInfo(const MachineFunction *MF,
}
// The value is valid until the next DBG_VALUE or clobber.
DotDebugLocEntries.push_back(DotDebugLocEntry(FLabel, SLabel, MLoc));
DotDebugLocEntries.push_back(DotDebugLocEntry(FLabel, SLabel, MLoc, Var));
}
DotDebugLocEntries.push_back(DotDebugLocEntry());
}
@ -2721,7 +2721,39 @@ void DwarfDebug::emitDebugLoc() {
} else {
Asm->OutStreamer.EmitSymbolValue(Entry.Begin, Size, 0);
Asm->OutStreamer.EmitSymbolValue(Entry.End, Size, 0);
Asm->EmitDwarfRegOp(Entry.Loc);
DIVariable DV(Entry.Variable);
if (DV.hasComplexAddress()) {
unsigned N = DV.getNumAddrElements();
unsigned i = 0;
Asm->OutStreamer.AddComment("Loc expr size");
if (N >= 2 && DV.getAddrElement(0) == DIBuilder::OpPlus) {
// If first address element is OpPlus then emit
// DW_OP_breg + Offset instead of DW_OP_reg + Offset.
MachineLocation Loc(Entry.Loc.getReg(), DV.getAddrElement(1));
Asm->EmitInt16(Asm->getDwarfRegOpSize(Loc) + N - 2);
Asm->EmitDwarfRegOp(Loc);
// Asm->EmitULEB128(DV.getAddrElement(1));
i = 2;
} else {
Asm->EmitInt16(Asm->getDwarfRegOpSize(Entry.Loc) + N);
Asm->EmitDwarfRegOp(Entry.Loc);
}
// Emit remaining complex address elements.
for (; i < N; ++i) {
uint64_t Element = DV.getAddrElement(i);
if (Element == DIBuilder::OpPlus) {
Asm->EmitInt8(dwarf::DW_OP_plus_uconst);
Asm->EmitULEB128(DV.getAddrElement(++i));
} else if (Element == DIBuilder::OpDeref)
Asm->EmitInt8(dwarf::DW_OP_deref);
else llvm_unreachable("unknown Opcode found in complex address");
}
} else {
Asm->OutStreamer.AddComment("Loc expr size");
Asm->EmitInt16(Asm->getDwarfRegOpSize(Entry.Loc));
Asm->EmitDwarfRegOp(Entry.Loc);
}
}
}
}

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@ -66,10 +66,12 @@ typedef struct DotDebugLocEntry {
const MCSymbol *Begin;
const MCSymbol *End;
MachineLocation Loc;
const MDNode *Variable;
bool Merged;
DotDebugLocEntry() : Begin(0), End(0), Merged(false) {}
DotDebugLocEntry(const MCSymbol *B, const MCSymbol *E, MachineLocation &L)
: Begin(B), End(E), Loc(L), Merged(false) {}
DotDebugLocEntry() : Begin(0), End(0), Variable(0), Merged(false) {}
DotDebugLocEntry(const MCSymbol *B, const MCSymbol *E, MachineLocation &L,
const MDNode *V)
: Begin(B), End(E), Loc(L), Variable(V), Merged(false) {}
/// Empty entries are also used as a trigger to emit temp label. Such
/// labels are referenced is used to find debug_loc offset for a given DIE.
bool isEmpty() { return Begin == 0 && End == 0; }

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@ -172,6 +172,47 @@ getDebugValueLocation(const MachineInstr *MI) const {
return Location;
}
/// getDwarfRegOpSize - get size required to emit given machine location using
/// dwarf encoding.
unsigned ARMAsmPrinter::getDwarfRegOpSize(const MachineLocation &MLoc) const {
const TargetRegisterInfo *RI = TM.getRegisterInfo();
if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
return AsmPrinter::getDwarfRegOpSize(MLoc);
else {
unsigned Reg = MLoc.getReg();
if (Reg >= ARM::S0 && Reg <= ARM::S31) {
assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
// S registers are described as bit-pieces of a register
// S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
// S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
unsigned SReg = Reg - ARM::S0;
unsigned Rx = 256 + (SReg >> 1);
OutStreamer.AddComment("Loc expr size");
// DW_OP_regx + ULEB + DW_OP_bit_piece + ULEB + ULEB
// 1 + ULEB(Rx) + 1 + 1 + 1
return 4 + MCAsmInfo::getULEB128Size(Rx);
}
if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
// Q registers Q0-Q15 are described by composing two D registers together.
// Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1) DW_OP_piece(8)
unsigned QReg = Reg - ARM::Q0;
unsigned D1 = 256 + 2 * QReg;
unsigned D2 = D1 + 1;
OutStreamer.AddComment("Loc expr size");
// DW_OP_regx + ULEB + DW_OP_piece + ULEB(8) +
// DW_OP_regx + ULEB + DW_OP_piece + ULEB(8);
// 6 + ULEB(D1) + ULEB(D2)
return 6 + MCAsmInfo::getULEB128Size(D1) + MCAsmInfo::getULEB128Size(D2);
}
}
return 0;
}
/// EmitDwarfRegOp - Emit dwarf register operation.
void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
const TargetRegisterInfo *RI = TM.getRegisterInfo();

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@ -89,6 +89,10 @@ public:
MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
/// getDwarfRegOpSize - get size required to emit given machine location
/// using dwarf encoding.
virtual unsigned getDwarfRegOpSize(const MachineLocation &MLoc) const;
/// EmitDwarfRegOp - Emit dwarf register operation.
virtual void EmitDwarfRegOp(const MachineLocation &MLoc) const;

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@ -1,5 +1,5 @@
; RUN: llc -O0 -mtriple=arm-apple-darwin < %s | grep DW_OP_fbreg
; Use DW_OP_fbreg in variable's location expression if the variable is in a stack slot.
; RUN: llc -O0 -mtriple=arm-apple-darwin < %s | grep DW_OP_breg
; Use DW_OP_breg in variable's location expression if the variable is in a stack slot.
%struct.SVal = type { i8*, i32 }

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@ -1,5 +1,5 @@
; RUN: llc -O0 -mtriple=x86_64-apple-darwin < %s | grep DW_OP_fbreg
; Use DW_OP_fbreg in variable's location expression if the variable is in a stack slot.
; RUN: llc -O0 -mtriple=x86_64-apple-darwin < %s | grep DW_OP_breg7
; Use DW_OP_breg7 in variable's location expression if the variable is in a stack slot.
%struct.SVal = type { i8*, i32 }