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Revert "Differential Revision: http://reviews.llvm.org/D20557"
Author: Wei Ding <wei.ding2@amd.com>
Date: Tue Jun 7 19:04:44 2016 +0000
Differential Revision: http://reviews.llvm.org/D20557
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272044
91177308-0d34-0410-b5e6-96231b3b80d8
as it was breaking the bots.
This reverts commit r272044.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272056 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
parent
3f950e9262
commit
c2a7f10882
@ -36,12 +36,6 @@
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using namespace llvm;
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// -amdgpu-fast-fdiv - Command line option to enable faster 2.5 ulp fdiv.
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static cl::opt<bool> EnableAMDGPUFastFDIV(
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"amdgpu-fast-fdiv",
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cl::desc("Enable faster 2.5 ulp fdiv"),
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cl::init(false));
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static unsigned findFirstFreeSGPR(CCState &CCInfo) {
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unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
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for (unsigned Reg = 0; Reg < NumSGPRs; ++Reg) {
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@ -1947,11 +1941,8 @@ SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {
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}
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SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
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const SDNodeFlags *Flags = Op->getFlags();
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if (Flags->hasAllowReciprocal()) {
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if (SDValue FastLowered = LowerFastFDIV(Op, DAG))
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return FastLowered;
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}
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if (SDValue FastLowered = LowerFastFDIV(Op, DAG))
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return FastLowered;
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// This uses v_rcp_f32 which does not handle denormals. Let this hit a
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// selection error for now rather than do something incorrect.
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@ -1962,61 +1953,32 @@ SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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// faster 2.5 ulp fdiv when using -amdgpu-fast-fdiv flag
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if (EnableAMDGPUFastFDIV) {
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SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
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SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
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const APFloat K0Val(BitsToFloat(0x6f800000));
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const SDValue K0 = DAG.getConstantFP(K0Val, SL, MVT::f32);
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const APFloat K0Val(BitsToFloat(0x6f800000));
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const SDValue K0 = DAG.getConstantFP(K0Val, SL, MVT::f32);
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const APFloat K1Val(BitsToFloat(0x2f800000));
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const SDValue K1 = DAG.getConstantFP(K1Val, SL, MVT::f32);
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const APFloat K1Val(BitsToFloat(0x2f800000));
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const SDValue K1 = DAG.getConstantFP(K1Val, SL, MVT::f32);
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const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
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EVT SetCCVT =
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getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
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SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
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SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
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// TODO: Should this propagate fast-math-flags?
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r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
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SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
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SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
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return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
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}
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// Generates more precise fpdiv32.
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const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
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SDVTList ScaleVT = DAG.getVTList(MVT::f32, MVT::i1);
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SDValue DenominatorScaled = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, RHS, RHS, LHS);
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SDValue NumeratorScaled = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, LHS, RHS, LHS);
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SDValue ApproxRcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, DenominatorScaled);
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SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f32, DenominatorScaled);
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SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f32, NegDivScale0, ApproxRcp, One);
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SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f32, Fma0, ApproxRcp, ApproxRcp);
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SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, NumeratorScaled, Fma1);
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SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f32, NegDivScale0, Mul, NumeratorScaled);
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SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f32, Fma2, Fma1, Mul);
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SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f32, NegDivScale0, Fma3, NumeratorScaled);
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SDValue Scale = NumeratorScaled.getValue(1);
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SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f32, Fma4, Fma1, Fma3, Scale);
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return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f32, Fmas, RHS, LHS);
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EVT SetCCVT =
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getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
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SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
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SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
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// TODO: Should this propagate fast-math-flags?
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r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
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SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
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SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
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return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
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}
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SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
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@ -1,33 +1,19 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -amdgpu-fast-fdiv < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=I754 %s
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; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=UNSAFE-FP %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
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; These tests check that fdiv is expanded correctly and also test that the
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; scheduler is scheduling the RECIP_IEEE and MUL_IEEE instructions in separate
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; instruction groups.
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; These test check that fdiv using unsafe_fp_math, coarse fp div, and IEEE754 fp div.
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; FUNC-LABEL: {{^}}fdiv_f32:
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
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; UNSAFE-FP: v_rcp_f32
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; UNSAFE-FP: v_mul_f32_e32
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; SI-DAG: v_rcp_f32
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; SI-DAG: v_mul_f32
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; I754-DAG: v_div_scale_f32
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; I754-DAG: v_rcp_f32
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; I754-DAG: v_fma_f32
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; I754-DAG: v_mul_f32
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; I754-DAG: v_fma_f32
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; I754-DAG: v_div_fixup_f32
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define void @fdiv_f32(float addrspace(1)* %out, float %a, float %b) {
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entry:
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%0 = fdiv float %a, %b
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@ -35,55 +21,7 @@ entry:
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ret void
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}
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; FUNC-LABEL: {{^}}fdiv_f32_fast_math:
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
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; UNSAFE-FP: v_rcp_f32
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; UNSAFE-FP: v_mul_f32_e32
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; SI-DAG: v_rcp_f32
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; SI-DAG: v_mul_f32
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; I754-DAG: v_div_scale_f32
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; I754-DAG: v_rcp_f32
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; I754-DAG: v_fma_f32
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; I754-DAG: v_mul_f32
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; I754-DAG: v_fma_f32
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; I754-DAG: v_div_fixup_f32
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define void @fdiv_f32_fast_math(float addrspace(1)* %out, float %a, float %b) {
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entry:
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%0 = fdiv fast float %a, %b
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store float %0, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fdiv_f32_arcp_math:
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
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; UNSAFE-FP: v_rcp_f32
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; UNSAFE-FP: v_mul_f32_e32
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; SI-DAG: v_rcp_f32
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; SI-DAG: v_mul_f32
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; I754-DAG: v_div_scale_f32
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; I754-DAG: v_rcp_f32
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; I754-DAG: v_fma_f32
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; I754-DAG: v_mul_f32
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; I754-DAG: v_fma_f32
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; I754-DAG: v_div_fixup_f32
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define void @fdiv_f32_arcp_math(float addrspace(1)* %out, float %a, float %b) {
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entry:
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%0 = fdiv arcp float %a, %b
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store float %0, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fdiv_v2f32:
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
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@ -91,22 +29,10 @@ entry:
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
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; UNSAFE-FP: v_rcp_f32
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; UNSAFE-FP: v_rcp_f32
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; UNSAFE-FP: v_mul_f32_e32
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; UNSAFE-FP: v_mul_f32_e32
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; SI-DAG: v_rcp_f32
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; SI-DAG: v_mul_f32
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; SI-DAG: v_rcp_f32
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; SI-DAG: v_mul_f32
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; I754: v_div_scale_f32
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; I754: v_div_scale_f32
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; I754: v_div_scale_f32
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; I754: v_div_scale_f32
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; I754: v_div_fixup_f32
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; I754: v_div_fixup_f32
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define void @fdiv_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
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entry:
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%0 = fdiv <2 x float> %a, %b
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@ -114,65 +40,6 @@ entry:
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ret void
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}
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; FUNC-LABEL: {{^}}fdiv_v2f32_fast_math:
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
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; UNSAFE-FP: v_rcp_f32
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; UNSAFE-FP: v_rcp_f32
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; UNSAFE-FP: v_mul_f32_e32
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; UNSAFE-FP: v_mul_f32_e32
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; SI-DAG: v_rcp_f32
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; SI-DAG: v_mul_f32
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; SI-DAG: v_rcp_f32
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; SI-DAG: v_mul_f32
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; I754: v_div_scale_f32
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; I754: v_div_scale_f32
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; I754: v_div_scale_f32
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; I754: v_div_scale_f32
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; I754: v_div_fixup_f32
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; I754: v_div_fixup_f32
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define void @fdiv_v2f32_fast_math(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
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entry:
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%0 = fdiv fast <2 x float> %a, %b
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store <2 x float> %0, <2 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fdiv_v2f32_arcp_math:
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
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; UNSAFE-FP: v_rcp_f32
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; UNSAFE-FP: v_rcp_f32
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; UNSAFE-FP: v_mul_f32_e32
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; UNSAFE-FP: v_mul_f32_e32
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; SI-DAG: v_rcp_f32
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; SI-DAG: v_mul_f32
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; SI-DAG: v_rcp_f32
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; SI-DAG: v_mul_f32
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; I754: v_div_scale_f32
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; I754: v_div_scale_f32
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; I754: v_div_scale_f32
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; I754: v_div_scale_f32
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; I754: v_div_fixup_f32
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; I754: v_div_fixup_f32
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define void @fdiv_v2f32_arcp_math(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
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entry:
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%0 = fdiv arcp <2 x float> %a, %b
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store <2 x float> %0, <2 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fdiv_v4f32:
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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@ -183,15 +50,6 @@ entry:
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
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; UNSAFE-FP: v_rcp_f32_e32
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; UNSAFE-FP: v_rcp_f32_e32
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; UNSAFE-FP: v_rcp_f32_e32
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; UNSAFE-FP: v_rcp_f32_e32
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; UNSAFE-FP: v_mul_f32_e32
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; UNSAFE-FP: v_mul_f32_e32
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; UNSAFE-FP: v_mul_f32_e32
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; UNSAFE-FP: v_mul_f32_e32
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; SI-DAG: v_rcp_f32
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; SI-DAG: v_mul_f32
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; SI-DAG: v_rcp_f32
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@ -200,19 +58,6 @@ entry:
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; SI-DAG: v_mul_f32
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; SI-DAG: v_rcp_f32
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; SI-DAG: v_mul_f32
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; I754: v_div_scale_f32
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; I754: v_div_scale_f32
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; I754: v_div_scale_f32
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; I754: v_div_scale_f32
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; I754: v_div_scale_f32
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; I754: v_div_scale_f32
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; I754: v_div_scale_f32
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; I754: v_div_scale_f32
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; I754: v_div_fixup_f32
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; I754: v_div_fixup_f32
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; I754: v_div_fixup_f32
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; I754: v_div_fixup_f32
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define void @fdiv_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
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%a = load <4 x float>, <4 x float> addrspace(1) * %in
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@ -221,101 +66,3 @@ define void @fdiv_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)
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store <4 x float> %result, <4 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fdiv_v4f32_fast_math:
|
||||
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
||||
|
||||
; UNSAFE-FP: v_rcp_f32_e32
|
||||
; UNSAFE-FP: v_rcp_f32_e32
|
||||
; UNSAFE-FP: v_rcp_f32_e32
|
||||
; UNSAFE-FP: v_rcp_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_fixup_f32
|
||||
; I754: v_div_fixup_f32
|
||||
; I754: v_div_fixup_f32
|
||||
; I754: v_div_fixup_f32
|
||||
define void @fdiv_v4f32_fast_math(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
|
||||
%b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
|
||||
%a = load <4 x float>, <4 x float> addrspace(1) * %in
|
||||
%b = load <4 x float>, <4 x float> addrspace(1) * %b_ptr
|
||||
%result = fdiv fast <4 x float> %a, %b
|
||||
store <4 x float> %result, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}fdiv_v4f32_arcp_math:
|
||||
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
||||
|
||||
; UNSAFE-FP: v_rcp_f32_e32
|
||||
; UNSAFE-FP: v_rcp_f32_e32
|
||||
; UNSAFE-FP: v_rcp_f32_e32
|
||||
; UNSAFE-FP: v_rcp_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_fixup_f32
|
||||
; I754: v_div_fixup_f32
|
||||
; I754: v_div_fixup_f32
|
||||
; I754: v_div_fixup_f32
|
||||
define void @fdiv_v4f32_arcp_math(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
|
||||
%b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
|
||||
%a = load <4 x float>, <4 x float> addrspace(1) * %in
|
||||
%b = load <4 x float>, <4 x float> addrspace(1) * %b_ptr
|
||||
%result = fdiv arcp <4 x float> %a, %b
|
||||
store <4 x float> %result, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user