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AMDGPU/SI: Add MachineBasicBlock parameter to SIInstrInfo::insertWaitStates

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Summary: This makes it possible to insert nops at the end of blocks.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D18549

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265678 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2016-04-07 14:47:07 +00:00
parent 30c5dec16c
commit c2d9280e43
4 changed files with 8 additions and 6 deletions
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2
lib/Target/AMDGPU/SIInsertWaits.cpp
View File

@ -519,7 +519,7 @@ void SIInsertWaits::insertDPPWaitStates(MachineBasicBlock::iterator DPP,
continue;
if (DPP->readsRegister(Op.getReg(), TRI)) {
TII->insertWaitStates(DPP, WaitStates);
TII->insertWaitStates(*DPP->getParent(), DPP, WaitStates);
return;
}
}

5
lib/Target/AMDGPU/SIInstrInfo.cpp
View File

@ -801,7 +801,8 @@ unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
return TmpReg;
}
void SIInstrInfo::insertWaitStates(MachineBasicBlock::iterator MI,
void SIInstrInfo::insertWaitStates(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
int Count) const {
while (Count > 0) {
int Arg;
@ -810,7 +811,7 @@ void SIInstrInfo::insertWaitStates(MachineBasicBlock::iterator MI,
else
Arg = Count - 1;
Count -= 8;
BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
.addImm(Arg);
}
}

3
lib/Target/AMDGPU/SIInstrInfo.h
View File

@ -437,7 +437,8 @@ public:
void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
unsigned SavReg, unsigned IndexReg) const;
void insertWaitStates(MachineBasicBlock::iterator MI, int Count) const;
void insertWaitStates(MachineBasicBlock &MBB,MachineBasicBlock::iterator MI,
int Count) const;
/// \brief Returns the operand named \p Op. If \p MI does not have an
/// operand named \c Op, this function returns nullptr.

4
lib/Target/AMDGPU/SIRegisterInfo.cpp
View File

@ -414,7 +414,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
case AMDGPUSubtarget::SOUTHERN_ISLANDS:
// "VALU writes SGPR" -> "SMRD reads that SGPR" needs 4 wait states
// ("S_NOP 3") on SI
TII->insertWaitStates(MI, 4);
TII->insertWaitStates(*MBB, MI, 4);
break;
case AMDGPUSubtarget::SEA_ISLANDS:
break;
@ -422,7 +422,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
// "VALU writes SGPR -> VMEM reads that SGPR" needs 5 wait states
// ("S_NOP 4") on VI and later. This also applies to VALUs which write
// VCC, but we're unlikely to see VMEM use VCC.
TII->insertWaitStates(MI, 5);
TII->insertWaitStates(*MBB, MI, 5);
}
MI->eraseFromParent();