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Rip out 1.6ness, bump version # to 1.7cvs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24246 91177308-0d34-0410-b5e6-96231b3b80d8
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Chris Lattner
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@ -4,11 +4,11 @@
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<head>
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<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
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<link rel="stylesheet" href="llvm.css" type="text/css">
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<title>LLVM 1.6 Release Notes</title>
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<title>LLVM 1.7cvs Release Notes</title>
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</head>
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<body>
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<div class="doc_title">LLVM 1.6 Release Notes</div>
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<div class="doc_title">LLVM 1.7 Release Notes</div>
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<ol>
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<li><a href="#intro">Introduction</a></li>
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@ -32,10 +32,10 @@
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<div class="doc_text">
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<p>This document contains the release notes for the LLVM compiler
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infrastructure, release 1.6. Here we describe the status of LLVM, including any
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infrastructure, release 1.7. Here we describe the status of LLVM, including any
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known problems and major improvements from the previous release. The most
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up-to-date version of this document can be found on the <a
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href="http://llvm.org/releases/1.6/">LLVM 1.6 web site</a>. If you are
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href="http://llvm.org/releases/">LLVM releases web site</a>. If you are
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not reading this on the LLVM web pages, you should probably go there because
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this document may be updated after the release.</p>
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@ -71,181 +71,9 @@ out and it is now as well supported as Linux on X86.</p>
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<!--=========================================================================-->
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<div class="doc_subsection">
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<a name="newfeatures">New Features in LLVM 1.6</a>
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<a name="newfeatures">New Features in LLVM 1.7cvs</a>
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</div>
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<!--_________________________________________________________________________-->
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<div class="doc_subsubsection"><a name="iselgen">Instruction Selector
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Generation from Target Description</a></div>
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<div class="doc_text">
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<p>LLVM now includes support for auto-generating large portions of the
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instruction selectors from target descriptions. This allows us to
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write patterns in the target .td file, instead of writing lots of
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nasty C++ code. Most of the PowerPC instruction selector is now
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generated from the PowerPC target description files and other targets
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are adding support that will be live for LLVM 1.7.</p>
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<p>For example, here are some patterns used by the PowerPC backend. A
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floating-point multiply then subtract instruction (FMSUBS):</p>
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<div class="doc_code"><p>
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<tt>(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC), F4RC:$FRB))</tt>
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</p></div>
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<p>Exclusive-or by 16-bit immediate (XORI):</p>
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<div class="doc_code"><p>
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<tt>(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))</tt>
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</p></div>
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<p>Exclusive-or by 16-bit immediate shifted right 16-bits (XORIS):</p>
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<div class="doc_code"><p>
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<tt>(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))</tt>
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</p></div>
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<p>With these definitions, we teach the code generator how to combine these two
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instructions to xor an abitrary 32-bit immediate with the following
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definition. The first line specifies what to match (a xor with an arbitrary
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immediate) the second line specifies what to produce:</p>
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<div class="doc_code"><p>
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<pre>def : Pat<(xor GPRC:$in, imm:$imm),
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(XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
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</pre>
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</p></div>
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</div>
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<!--_________________________________________________________________________-->
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<div class="doc_subsubsection"><a name="sched">Instruction Scheduling
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Support</a></div>
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<div class="doc_text">
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<p>Instruction selectors using the refined <a
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href="CodeGenerator.html#instselect">instruction selection framework</a> can now
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use a simple pre-pass scheduler included with LLVM 1.6. This scheduler is
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currently simple (cannot be configured much by the targets), but will be
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extended in the future.</p>
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</div>
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<!--_________________________________________________________________________-->
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<div class="doc_subsubsection"><a name="subtarget">Code Generator Subtarget
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Support</a></div>
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<div class="doc_text">
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<p>It is now straight-forward to parameterize a target implementation, and
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provide a mapping from CPU names to sets of target parameters. LLC now supports
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a <tt>-mcpu=cpu</tt> option that lets you choose a subtarget by CPU name: use
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"<tt>llvm-as < /dev/null | llc -march=XXX -mcpu=help</tt>" to get a list of
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supported CPUs for target "XXX". It also provides a
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<tt>-mattr=+attr1,-attr2</tt> option that can be used to control individual
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features of a target (the previous command will list available features as
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well).</p>
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<p>This functionality is nice when you want tell LLC something like "compile to
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code that is specialized for the PowerPC G5, but doesn't use altivec code. In
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this case, using "<tt>llc -march=ppc32 -mcpu=g5 -mattr=-altivec</tt>".</p>
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</div>
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<!--_________________________________________________________________________-->
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<div class="doc_subsubsection"><a name="jitlock">Other New Features</a></div>
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<div class="doc_text">
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<ol>
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<li>The JIT now uses mutexes to protect its internal data structures. This
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allows multi-threaded programs to be run from the JIT or interpreter without
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corruption of the internal data structures. See
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<a href="http://llvm.org/PR418">PR418</a> and
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<a href="http://llvm.org/PR540">PR540</a> for the details.
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</li>
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<li>LLVM on Win32 <a href="http://llvm.org/PR614">no longer requires sed,
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flex, or bison when compiling with Visual C++</a>.</li>
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<li>The llvm-test suite can now use the NAG Fortran to C compiler to compile
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SPEC FP programs if available (allowing us to test all of SPEC'95 &
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2000).</li>
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<li>When bugpoint is grinding away and the user hits ctrl-C, it now
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gracefully stops and gives what it has reduced so far, instead of
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giving up completely. In addition, <a href="http://llvm.org/PR576">the JIT
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debugging mode of bugpoint is much faster</a>.</li>
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<li>LLVM now includes Xcode project files in the llvm/Xcode directory.</li>
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<li>LLVM now supports Mac OS X on Intel.</li>
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<li>LLVM now builds cleanly with GCC 4.1.</li>
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</ol>
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</div>
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<!--=========================================================================-->
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<div class="doc_subsection">
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<a name="codequality">Code Quality Improvements in LLVM 1.6</a>
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</div>
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<div class="doc_text">
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<ol>
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<li>The <tt>-globalopt</tt> pass can now statically evaluate C++ static
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constructors when they are simple enough. For example, it can
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now statically initialize "<tt>struct X { int a; X() : a(4) {} } g;</tt>".
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</li>
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<li>The Loop Strength Reduction pass has been completely rewritten, is far
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more aggressive, and is turned on by default in the RISC targets. On PPC,
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we find that it often speeds up programs from 10-40% depending on the
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program.</li>
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<li>The code produced when exception handling is enabled is far more
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efficient in some cases, particularly on Mac OS X.</li>
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</ol>
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</div>
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<!--=========================================================================-->
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<div class="doc_subsection">
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<a name="codequality">Code Generator Improvements in LLVM 1.6</a>
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</div>
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<div class="doc_text">
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<ol>
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<li>The Alpha backend is substantially more stable and robust than in LLVM 1.5.
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For example, it now fully supports varargs functions. The Alpha backend
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also now features beta JIT support.</li>
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<li>The code generator contains a new component, the DAG Combiner. This allows
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us to optimize lowered code (e.g. after 64-bit operations have been lowered
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to use 32-bit registers on 32-bit targets) and do fine-grained bit-twiddling
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optimizations for the backend.</li>
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<li>The SelectionDAG infrastructure is far more capable and mature, able to
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handle many new target peculiarities in a target-independent way.</li>
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<li>The default <a href="http://llvm.org/PR547">register allocator is now far
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faster on some testcases</a>,
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particularly on targets with a large number of registers (e.g. IA64
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and PPC).</li>
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</ol>
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</div>
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<!--=========================================================================-->
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<div class="doc_subsection">
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<a name="bugfix">Significant Bugs Fixed in LLVM 1.6</a>
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</div>
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<div class="doc_text">
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<ol>
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<li>A vast number of bugs have been fixed in the PowerPC backend and in
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llvm-gcc when configured for Mac OS X (particularly relating to ABI
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issues). For example:
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<a href="http://llvm.org/PR603">PR449</a>,
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<a href="http://llvm.org/PR594">PR594</a>,
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<a href="http://llvm.org/PR603">PR603</a>,
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<a href="http://llvm.org/PR609">PR609</a>,
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<a href="http://llvm.org/PR630">PR630</a>,
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<a href="http://llvm.org/PR643">PR643</a>,
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and several others without bugzilla bugs.</li>
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<li>Several bugs in tail call support have been fixed.</li>
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<li><a href="http://llvm.org/PR608">configure does not correctly detect gcc
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version on cygwin</a>.</li>
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<li>Many many other random bugs have been fixed. Query <a
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href="http://llvm.org/bugs">our bugzilla</a> with a target of 1.6 for more
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information.</li>
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</ol>
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</div>
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<!-- *********************************************************************** -->
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<div class="doc_section">
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