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NEON VLD3(multiple 3-element structures) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148745 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
2c6d0f2625
commit
c387fc66bd
@ -124,6 +124,15 @@ def VecListTwoQAsmOperand : AsmOperandClass {
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def VecListTwoQ : RegisterOperand<DPR, "printVectorListTwoSpaced"> {
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let ParserMatchClass = VecListTwoQAsmOperand;
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}
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// Register list of three D registers spaced by 2 (three Q registers).
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def VecListThreeQAsmOperand : AsmOperandClass {
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let Name = "VecListThreeQ";
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let ParserMethod = "parseVectorList";
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let RenderMethod = "addVecListOperands";
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}
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def VecListThreeQ : RegisterOperand<DPR, "printVectorListThreeSpaced"> {
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let ParserMatchClass = VecListThreeQAsmOperand;
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}
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// Register list of one D register, with "all lanes" subscripting.
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def VecListOneDAllLanesAsmOperand : AsmOperandClass {
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@ -6017,6 +6026,67 @@ def VLD3LNqWB_register_Asm_32 :
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(ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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// VLD3 multiple structurepseudo-instructions. These need special handling for
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// the vector operands that the normal instructions don't yet model.
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// FIXME: Remove these when the register classes and instructions are updated.
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def VLD3dAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
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(ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
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def VLD3dAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
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(ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
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def VLD3dAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
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(ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
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def VLD3qAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
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(ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
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def VLD3qAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
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(ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
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def VLD3qAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
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(ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
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def VLD3dWB_fixed_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
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(ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
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def VLD3dWB_fixed_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
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(ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
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def VLD3dWB_fixed_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
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(ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
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def VLD3qWB_fixed_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
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(ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
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def VLD3qWB_fixed_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
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(ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
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def VLD3qWB_fixed_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
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(ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
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def VLD3dWB_register_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
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(ins VecListThreeD:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD3dWB_register_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
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(ins VecListThreeD:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD3dWB_register_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
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(ins VecListThreeD:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD3qWB_register_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
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(ins VecListThreeQ:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD3qWB_register_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
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(ins VecListThreeQ:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD3qWB_register_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
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(ins VecListThreeQ:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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// VMOV takes an optional datatype suffix
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defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
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(VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
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@ -1101,6 +1101,11 @@ public:
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return VectorList.Count == 2;
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}
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bool isVecListThreeQ() const {
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if (!isDoubleSpacedVectorList()) return false;
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return VectorList.Count == 3;
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}
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bool isSingleSpacedVectorAllLanes() const {
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return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
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}
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@ -5376,6 +5381,62 @@ static unsigned getRealVLDLNOpcode(unsigned Opc, unsigned &Spacing) {
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case ARM::VLD3LNqAsm_32:
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Spacing = 2;
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return ARM::VLD3LNq32;
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// VLD3
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case ARM::VLD3dWB_fixed_Asm_8:
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Spacing = 1;
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return ARM::VLD3d8_UPD;
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case ARM::VLD3dWB_fixed_Asm_16:
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Spacing = 1;
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return ARM::VLD3d16_UPD;
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case ARM::VLD3dWB_fixed_Asm_32:
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Spacing = 1;
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return ARM::VLD3d32_UPD;
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case ARM::VLD3qWB_fixed_Asm_8:
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Spacing = 2;
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return ARM::VLD3q8_UPD;
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case ARM::VLD3qWB_fixed_Asm_16:
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Spacing = 2;
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return ARM::VLD3q16_UPD;
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case ARM::VLD3qWB_fixed_Asm_32:
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Spacing = 2;
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return ARM::VLD3q32_UPD;
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case ARM::VLD3dWB_register_Asm_8:
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Spacing = 1;
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return ARM::VLD3d8_UPD;
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case ARM::VLD3dWB_register_Asm_16:
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Spacing = 1;
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return ARM::VLD3d16_UPD;
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case ARM::VLD3dWB_register_Asm_32:
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Spacing = 1;
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return ARM::VLD3d32_UPD;
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case ARM::VLD3qWB_register_Asm_8:
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Spacing = 2;
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return ARM::VLD3q8_UPD;
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case ARM::VLD3qWB_register_Asm_16:
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Spacing = 2;
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return ARM::VLD3q16_UPD;
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case ARM::VLD3qWB_register_Asm_32:
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Spacing = 2;
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return ARM::VLD3q32_UPD;
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case ARM::VLD3dAsm_8:
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Spacing = 1;
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return ARM::VLD3d8;
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case ARM::VLD3dAsm_16:
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Spacing = 1;
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return ARM::VLD3d16;
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case ARM::VLD3dAsm_32:
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Spacing = 1;
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return ARM::VLD3d32;
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case ARM::VLD3qAsm_8:
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Spacing = 2;
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return ARM::VLD3q8;
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case ARM::VLD3qAsm_16:
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Spacing = 2;
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return ARM::VLD3q16;
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case ARM::VLD3qAsm_32:
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Spacing = 2;
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return ARM::VLD3q32;
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}
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}
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@ -5588,7 +5649,7 @@ processInstruction(MCInst &Inst,
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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Spacing * 2));
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TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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TmpInst.addOperand(Inst.getOperand(3)); // alignment
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@ -5597,7 +5658,7 @@ processInstruction(MCInst &Inst,
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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Spacing * 2));
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TmpInst.addOperand(Inst.getOperand(1)); // lane
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TmpInst.addOperand(Inst.getOperand(5)); // CondCode
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TmpInst.addOperand(Inst.getOperand(6));
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@ -5667,7 +5728,7 @@ processInstruction(MCInst &Inst,
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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Spacing * 2));
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TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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TmpInst.addOperand(Inst.getOperand(3)); // alignment
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@ -5676,7 +5737,7 @@ processInstruction(MCInst &Inst,
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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Spacing * 2));
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TmpInst.addOperand(Inst.getOperand(1)); // lane
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TmpInst.addOperand(Inst.getOperand(4)); // CondCode
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TmpInst.addOperand(Inst.getOperand(5));
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@ -5742,14 +5803,14 @@ processInstruction(MCInst &Inst,
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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Spacing * 2));
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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TmpInst.addOperand(Inst.getOperand(3)); // alignment
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TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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Spacing * 2));
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TmpInst.addOperand(Inst.getOperand(1)); // lane
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TmpInst.addOperand(Inst.getOperand(4)); // CondCode
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TmpInst.addOperand(Inst.getOperand(5));
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@ -5757,6 +5818,77 @@ processInstruction(MCInst &Inst,
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return true;
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}
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// VLD3 multiple 3-element structure instructions.
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case ARM::VLD3dAsm_8:
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case ARM::VLD3dAsm_16:
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case ARM::VLD3dAsm_32:
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case ARM::VLD3qAsm_8:
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case ARM::VLD3qAsm_16:
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case ARM::VLD3qAsm_32: {
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MCInst TmpInst;
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unsigned Spacing;
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TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(Inst.getOperand(1)); // Rn
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TmpInst.addOperand(Inst.getOperand(2)); // alignment
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TmpInst.addOperand(Inst.getOperand(3)); // CondCode
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TmpInst.addOperand(Inst.getOperand(4));
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Inst = TmpInst;
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return true;
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}
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case ARM::VLD3dWB_fixed_Asm_8:
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case ARM::VLD3dWB_fixed_Asm_16:
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case ARM::VLD3dWB_fixed_Asm_32:
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case ARM::VLD3qWB_fixed_Asm_8:
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case ARM::VLD3qWB_fixed_Asm_16:
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case ARM::VLD3qWB_fixed_Asm_32: {
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MCInst TmpInst;
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unsigned Spacing;
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TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(Inst.getOperand(1)); // Rn
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TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
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TmpInst.addOperand(Inst.getOperand(2)); // alignment
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TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
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TmpInst.addOperand(Inst.getOperand(3)); // CondCode
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TmpInst.addOperand(Inst.getOperand(4));
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Inst = TmpInst;
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return true;
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}
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case ARM::VLD3dWB_register_Asm_8:
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case ARM::VLD3dWB_register_Asm_16:
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case ARM::VLD3dWB_register_Asm_32:
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case ARM::VLD3qWB_register_Asm_8:
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case ARM::VLD3qWB_register_Asm_16:
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case ARM::VLD3qWB_register_Asm_32: {
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MCInst TmpInst;
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unsigned Spacing;
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TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(Inst.getOperand(1)); // Rn
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TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
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TmpInst.addOperand(Inst.getOperand(2)); // alignment
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TmpInst.addOperand(Inst.getOperand(3)); // Rm
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TmpInst.addOperand(Inst.getOperand(4)); // CondCode
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TmpInst.addOperand(Inst.getOperand(5));
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Inst = TmpInst;
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return true;
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}
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// Handle the Thumb2 mode MOV complex aliases.
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case ARM::t2MOVsr:
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case ARM::t2MOVSsr: {
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@ -1086,3 +1086,13 @@ void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}";
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}
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void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
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unsigned OpNum,
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raw_ostream &O) {
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// Normally, it's not safe to use register enum values directly with
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// addition to get the next register, but for VFP registers, the
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// sort order is guaranteed because they're all of the form D<n>.
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O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "}";
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}
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@ -143,6 +143,8 @@ public:
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raw_ostream &O);
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void printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printVectorListThreeSpaced(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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};
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} // end namespace llvm
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@ -154,25 +154,46 @@
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@ CHECK: vld2.32 {d14, d15, d16, d17}, [r0, :256], r6 @ encoding: [0xb6,0xe3,0x20,0xf4]
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@ vld3.8 {d16, d17, d18}, [r0, :64]
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@ vld3.16 {d16, d17, d18}, [r0]
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@ vld3.32 {d16, d17, d18}, [r0]
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@ vld3.8 {d16, d18, d20}, [r0, :64]!
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@ vld3.8 {d17, d19, d21}, [r0, :64]!
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@ vld3.16 {d16, d18, d20}, [r0]!
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@ vld3.16 {d17, d19, d21}, [r0]!
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@ vld3.32 {d16, d18, d20}, [r0]!
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@ vld3.32 {d17, d19, d21}, [r0]!
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vld3.8 {d16, d17, d18}, [r1]
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vld3.16 {d6, d7, d8}, [r2]
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vld3.32 {d1, d2, d3}, [r3]
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vld3.8 {d16, d18, d20}, [r0, :64]
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vld3.u16 {d27, d29, d31}, [r4]
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vld3.i32 {d6, d8, d10}, [r5]
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@ FIXME: vld3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x60,0xf4]
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@ FIXME: vld3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x60,0xf4]
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@ FIXME: vld3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x60,0xf4]
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@ FIXME: vld3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x60,0xf4]
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@ FIXME: vld3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x60,0xf4]
|
||||
@ FIXME: vld3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x60,0xf4]
|
||||
@ FIXME: vld3.16 {d17, d19, d21}, [r0]! @ encoding: [0x4d,0x15,0x60,0xf4]
|
||||
@ FIXME: vld3.32 {d16, d18, d20}, [r0]! @ encoding: [0x8d,0x05,0x60,0xf4]
|
||||
@ FIXME: vld3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x60,0xf4]
|
||||
vld3.i8 {d12, d13, d14}, [r6], r1
|
||||
vld3.i16 {d11, d12, d13}, [r7], r2
|
||||
vld3.u32 {d2, d3, d4}, [r8], r3
|
||||
vld3.8 {d4, d6, d8}, [r9], r4
|
||||
vld3.u16 {d14, d16, d18}, [r9], r4
|
||||
vld3.i32 {d16, d18, d20}, [r10], r5
|
||||
|
||||
vld3.p8 {d6, d7, d8}, [r8]!
|
||||
vld3.16 {d9, d10, d11}, [r7]!
|
||||
vld3.f32 {d1, d2, d3}, [r6]!
|
||||
vld3.8 {d16, d18, d20}, [r0, :64]!
|
||||
vld3.p16 {d20, d22, d24}, [r5]!
|
||||
vld3.32 {d5, d7, d9}, [r4]!
|
||||
|
||||
|
||||
@ CHECK: vld3.8 {d16, d17, d18}, [r1] @ encoding: [0x0f,0x04,0x61,0xf4]
|
||||
@ CHECK: vld3.16 {d6, d7, d8}, [r2] @ encoding: [0x4f,0x64,0x22,0xf4]
|
||||
@ CHECK: vld3.32 {d1, d2, d3}, [r3] @ encoding: [0x8f,0x14,0x23,0xf4]
|
||||
@ CHECK: vld3.8 {d16, d18, d20}, [r0, :64] @ encoding: [0x1f,0x05,0x60,0xf4]
|
||||
@ CHECK: vld3.16 {d27, d29, d31}, [r4] @ encoding: [0x4f,0xb5,0x64,0xf4]
|
||||
@ CHECK: vld3.32 {d6, d8, d10}, [r5] @ encoding: [0x8f,0x65,0x25,0xf4]
|
||||
@ CHECK: vld3.8 {d12, d13, d14}, [r6], r1 @ encoding: [0x01,0xc4,0x26,0xf4]
|
||||
@ CHECK: vld3.16 {d11, d12, d13}, [r7], r2 @ encoding: [0x42,0xb4,0x27,0xf4]
|
||||
@ CHECK: vld3.32 {d2, d3, d4}, [r8], r3 @ encoding: [0x83,0x24,0x28,0xf4]
|
||||
@ CHECK: vld3.8 {d4, d6, d8}, [r9], r4 @ encoding: [0x04,0x45,0x29,0xf4]
|
||||
@ CHECK: vld3.16 {d14, d16, d18}, [r9], r4 @ encoding: [0x44,0xe5,0x29,0xf4]
|
||||
@ CHECK: vld3.32 {d16, d18, d20}, [r10], r5 @ encoding: [0x85,0x05,0x6a,0xf4]
|
||||
@ CHECK: vld3.8 {d6, d7, d8}, [r8]! @ encoding: [0x0d,0x64,0x28,0xf4]
|
||||
@ CHECK: vld3.16 {d9, d10, d11}, [r7]! @ encoding: [0x4d,0x94,0x27,0xf4]
|
||||
@ CHECK: vld3.32 {d1, d2, d3}, [r6]! @ encoding: [0x8d,0x14,0x26,0xf4]
|
||||
@ CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x60,0xf4]
|
||||
@ CHECK: vld3.16 {d20, d22, d24}, [r5]! @ encoding: [0x4d,0x45,0x65,0xf4]
|
||||
@ CHECK: vld3.32 {d5, d7, d9}, [r4]! @ encoding: [0x8d,0x55,0x24,0xf4]
|
||||
|
||||
|
||||
@ vld4.8 {d16, d17, d18, d19}, [r0, :64]
|
||||
@ -260,17 +281,39 @@
|
||||
@ CHECK: vld2.32 {d22[], d24[]}, [r6], r4 @ encoding: [0xa4,0x6d,0xe6,0xf4]
|
||||
|
||||
|
||||
@ vld3.8 {d16[1], d17[1], d18[1]}, [r0]
|
||||
@ vld3.16 {d16[1], d17[1], d18[1]}, [r0]
|
||||
@ vld3.32 {d16[1], d17[1], d18[1]}, [r0]
|
||||
@ vld3.16 {d16[1], d18[1], d20[1]}, [r0]
|
||||
@ vld3.32 {d17[1], d19[1], d21[1]}, [r0]
|
||||
vld3.8 {d16[1], d17[1], d18[1]}, [r1]
|
||||
vld3.16 {d6[1], d7[1], d8[1]}, [r2]
|
||||
vld3.32 {d1[1], d2[1], d3[1]}, [r3]
|
||||
vld3.u16 {d27[2], d29[2], d31[2]}, [r4]
|
||||
vld3.i32 {d6[0], d8[0], d10[0]}, [r5]
|
||||
|
||||
@ FIXME: vld3.8 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x2f,0x02,0xe0,0xf4]
|
||||
@ FIXME: vld3.16 {d16[1], d17[1], d18[1]}, [r0]@ encoding: [0x4f,0x06,0xe0,0xf4]
|
||||
@ FIXME: vld3.32 {d16[1], d17[1], d18[1]}, [r0]@ encoding: [0x8f,0x0a,0xe0,0xf4]
|
||||
@ FIXME: vld3.16 {d16[1], d18[1], d20[1]}, [r0]@ encoding: [0x6f,0x06,0xe0,0xf4]
|
||||
@ FIXME: vld3.32 {d17[1], d19[1], d21[1]}, [r0]@ encoding: [0xcf,0x1a,0xe0,0xf4]
|
||||
vld3.i8 {d12[3], d13[3], d14[3]}, [r6], r1
|
||||
vld3.i16 {d11[2], d12[2], d13[2]}, [r7], r2
|
||||
vld3.u32 {d2[1], d3[1], d4[1]}, [r8], r3
|
||||
vld3.u16 {d14[2], d16[2], d18[2]}, [r9], r4
|
||||
vld3.i32 {d16[0], d18[0], d20[0]}, [r10], r5
|
||||
|
||||
vld3.p8 {d6[6], d7[6], d8[6]}, [r8]!
|
||||
vld3.16 {d9[2], d10[2], d11[2]}, [r7]!
|
||||
vld3.f32 {d1[1], d2[1], d3[1]}, [r6]!
|
||||
vld3.p16 {d20[2], d22[2], d24[2]}, [r5]!
|
||||
vld3.32 {d5[0], d7[0], d9[0]}, [r4]!
|
||||
|
||||
@ CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r1] @ encoding: [0x2f,0x02,0xe1,0xf4]
|
||||
@ CHECK: vld3.16 {d6[1], d7[1], d8[1]}, [r2] @ encoding: [0x4f,0x66,0xa2,0xf4]
|
||||
@ CHECK: vld3.32 {d1[1], d2[1], d3[1]}, [r3] @ encoding: [0x8f,0x1a,0xa3,0xf4]
|
||||
@ CHECK: vld3.16 {d27[2], d29[2], d31[2]}, [r4] @ encoding: [0xaf,0xb6,0xe4,0xf4]
|
||||
@ CHECK: vld3.32 {d6[0], d8[0], d10[0]}, [r5] @ encoding: [0x4f,0x6a,0xa5,0xf4]
|
||||
@ CHECK: vld3.8 {d12[3], d13[3], d14[3]}, [r6], r1 @ encoding: [0x61,0xc2,0xa6,0xf4]
|
||||
@ CHECK: vld3.16 {d11[2], d12[2], d13[2]}, [r7], r2 @ encoding: [0x82,0xb6,0xa7,0xf4]
|
||||
@ CHECK: vld3.32 {d2[1], d3[1], d4[1]}, [r8], r3 @ encoding: [0x83,0x2a,0xa8,0xf4]
|
||||
@ CHECK: vld3.16 {d14[2], d16[2], d18[2]}, [r9], r4 @ encoding: [0xa4,0xe6,0xa9,0xf4]
|
||||
@ CHECK: vld3.32 {d16[0], d18[0], d20[0]}, [r10], r5 @ encoding: [0x45,0x0a,0xea,0xf4]
|
||||
@ CHECK: vld3.8 {d6[6], d7[6], d8[6]}, [r8]! @ encoding: [0xcd,0x62,0xa8,0xf4]
|
||||
@ CHECK: vld3.16 {d9[2], d10[2], d11[2]}, [r7]! @ encoding: [0x8d,0x96,0xa7,0xf4]
|
||||
@ CHECK: vld3.32 {d1[1], d2[1], d3[1]}, [r6]! @ encoding: [0x8d,0x1a,0xa6,0xf4]
|
||||
@ CHECK: vld3.16 {d20[2], d21[2], d22[2]}, [r5]! @ encoding: [0xad,0x46,0xe5,0xf4]
|
||||
@ CHECK: vld3.32 {d5[0], d7[0], d9[0]}, [r4]! @ encoding: [0x4d,0x5a,0xa4,0xf4]
|
||||
|
||||
|
||||
@ vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
|
||||
|
||||
@ -133,41 +133,6 @@
|
||||
@ CHECK: vst2.32 {d5[0], d7[0]}, [r4, :64], r7 @ encoding: [0x57,0x59,0x84,0xf4]
|
||||
|
||||
|
||||
vld3.8 {d16[1], d17[1], d18[1]}, [r1]
|
||||
vld3.16 {d6[1], d7[1], d8[1]}, [r2]
|
||||
vld3.32 {d1[1], d2[1], d3[1]}, [r3]
|
||||
vld3.u16 {d27[2], d29[2], d31[2]}, [r4]
|
||||
vld3.i32 {d6[0], d8[0], d10[0]}, [r5]
|
||||
|
||||
vld3.i8 {d12[3], d13[3], d14[3]}, [r6], r1
|
||||
vld3.i16 {d11[2], d12[2], d13[2]}, [r7], r2
|
||||
vld3.u32 {d2[1], d3[1], d4[1]}, [r8], r3
|
||||
vld3.u16 {d14[2], d16[2], d18[2]}, [r9], r4
|
||||
vld3.i32 {d16[0], d18[0], d20[0]}, [r10], r5
|
||||
|
||||
vld3.p8 {d6[6], d7[6], d8[6]}, [r8]!
|
||||
vld3.16 {d9[2], d10[2], d11[2]}, [r7]!
|
||||
vld3.f32 {d1[1], d2[1], d3[1]}, [r6]!
|
||||
vld3.p16 {d20[2], d22[2], d24[2]}, [r5]!
|
||||
vld3.32 {d5[0], d7[0], d9[0]}, [r4]!
|
||||
|
||||
@ CHECK: vld3.8 {d16[1], d17[1], d17[1]}, [r1] @ encoding: [0x2f,0x02,0xe1,0xf4]
|
||||
@ CHECK: vld3.16 {d6[1], d7[1], d7[1]}, [r2] @ encoding: [0x4f,0x66,0xa2,0xf4]
|
||||
@ CHECK: vld3.32 {d1[1], d2[1], d2[1]}, [r3] @ encoding: [0x8f,0x1a,0xa3,0xf4]
|
||||
@ CHECK: vld3.16 {d27[2], d29[2], d29[2]}, [r4] @ encoding: [0xaf,0xb6,0xe4,0xf4]
|
||||
@ CHECK: vld3.32 {d6[0], d8[0], d8[0]}, [r5] @ encoding: [0x4f,0x6a,0xa5,0xf4]
|
||||
@ CHECK: vld3.8 {d12[3], d13[3], d13[3]}, [r6], r1 @ encoding: [0x61,0xc2,0xa6,0xf4]
|
||||
@ CHECK: vld3.16 {d11[2], d12[2], d12[2]}, [r7], r2 @ encoding: [0x82,0xb6,0xa7,0xf4]
|
||||
@ CHECK: vld3.32 {d2[1], d3[1], d3[1]}, [r8], r3 @ encoding: [0x83,0x2a,0xa8,0xf4]
|
||||
@ CHECK: vld3.16 {d14[2], d16[2], d16[2]}, [r9], r4 @ encoding: [0xa4,0xe6,0xa9,0xf4]
|
||||
@ CHECK: vld3.32 {d16[0], d18[0], d18[0]}, [r10], r5 @ encoding: [0x45,0x0a,0xea,0xf4]
|
||||
@ CHECK: vld3.8 {d6[6], d7[6], d7[6]}, [r8]! @ encoding: [0xcd,0x62,0xa8,0xf4]
|
||||
@ CHECK: vld3.16 {d9[2], d10[2], d10[2]}, [r7]! @ encoding: [0x8d,0x96,0xa7,0xf4]
|
||||
@ CHECK: vld3.32 {d1[1], d2[1], d2[1]}, [r6]! @ encoding: [0x8d,0x1a,0xa6,0xf4]
|
||||
@ CHECK: vld3.16 {d20[2], d21[2], d21[2]}, [r5]! @ encoding: [0xad,0x46,0xe5,0xf4]
|
||||
@ CHECK: vld3.32 {d5[0], d7[0], d7[0]}, [r4]! @ encoding: [0x4d,0x5a,0xa4,0xf4]
|
||||
|
||||
|
||||
@ vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
|
||||
@ vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]
|
||||
@ vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user