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[mips] [IAS] Store the expandLoadImm destination register in a variable. NFC.

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Summary: This removes multiple calls to getReg() and saves us column space in the source file.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8924

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235978 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Toma Tabacu 2015-04-28 12:04:53 +00:00
parent 716c5d8a30
commit c3adf30a03
1 changed files with 12 additions and 11 deletions
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23
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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@ -1713,6 +1713,7 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
assert(RegOp.isReg() && "expected register operand kind"); assert(RegOp.isReg() && "expected register operand kind");
int64_t ImmValue = ImmOp.getImm(); int64_t ImmValue = ImmOp.getImm();
unsigned Reg = RegOp.getReg();
tmpInst.setLoc(IDLoc); tmpInst.setLoc(IDLoc);
// FIXME: gas has a special case for values that are 000...1111, which // FIXME: gas has a special case for values that are 000...1111, which
// becomes a li -1 and then a dsrl // becomes a li -1 and then a dsrl
@ -1720,7 +1721,7 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
// For unsigned and positive signed 16-bit values (0 <= j <= 65535): // For unsigned and positive signed 16-bit values (0 <= j <= 65535):
// li d,j => ori d,$zero,j // li d,j => ori d,$zero,j
tmpInst.setOpcode(Mips::ORi); tmpInst.setOpcode(Mips::ORi);
tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg())); tmpInst.addOperand(MCOperand::CreateReg(Reg));
tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO)); tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
tmpInst.addOperand(MCOperand::CreateImm(ImmValue)); tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
Instructions.push_back(tmpInst); Instructions.push_back(tmpInst);
@ -1728,7 +1729,7 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
// For negative signed 16-bit values (-32768 <= j < 0): // For negative signed 16-bit values (-32768 <= j < 0):
// li d,j => addiu d,$zero,j // li d,j => addiu d,$zero,j
tmpInst.setOpcode(Mips::ADDiu); tmpInst.setOpcode(Mips::ADDiu);
tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg())); tmpInst.addOperand(MCOperand::CreateReg(Reg));
tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO)); tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
tmpInst.addOperand(MCOperand::CreateImm(ImmValue)); tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
Instructions.push_back(tmpInst); Instructions.push_back(tmpInst);
@ -1737,10 +1738,10 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
// li d,j => lui d,hi16(j) // li d,j => lui d,hi16(j)
// ori d,d,lo16(j) // ori d,d,lo16(j)
tmpInst.setOpcode(Mips::LUi); tmpInst.setOpcode(Mips::LUi);
tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg())); tmpInst.addOperand(MCOperand::CreateReg(Reg));
tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16)); tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
Instructions.push_back(tmpInst); Instructions.push_back(tmpInst);
createShiftOr<0, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions); createShiftOr<0, false>(ImmValue, Reg, IDLoc, Instructions);
} else if ((ImmValue & (0xffffLL << 48)) == 0) { } else if ((ImmValue & (0xffffLL << 48)) == 0) {
if (!isGP64bit()) { if (!isGP64bit()) {
Error(IDLoc, "instruction requires a 64-bit architecture"); Error(IDLoc, "instruction requires a 64-bit architecture");
@ -1761,12 +1762,12 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
// dsll d,d,16 // dsll d,d,16
// ori d,d,lo16(lo32(j)) // ori d,d,lo16(lo32(j))
tmpInst.setOpcode(Mips::LUi); tmpInst.setOpcode(Mips::LUi);
tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg())); tmpInst.addOperand(MCOperand::CreateReg(Reg));
tmpInst.addOperand( tmpInst.addOperand(
MCOperand::CreateImm((ImmValue & (0xffffLL << 32)) >> 32)); MCOperand::CreateImm((ImmValue & (0xffffLL << 32)) >> 32));
Instructions.push_back(tmpInst); Instructions.push_back(tmpInst);
createShiftOr<16, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions); createShiftOr<16, false>(ImmValue, Reg, IDLoc, Instructions);
createShiftOr<0, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions); createShiftOr<0, true>(ImmValue, Reg, IDLoc, Instructions);
} else { } else {
if (!isGP64bit()) { if (!isGP64bit()) {
Error(IDLoc, "instruction requires a 64-bit architecture"); Error(IDLoc, "instruction requires a 64-bit architecture");
@ -1788,13 +1789,13 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
// dsll d,d,16 // dsll d,d,16
// ori d,d,lo16(lo32(j)) // ori d,d,lo16(lo32(j))
tmpInst.setOpcode(Mips::LUi); tmpInst.setOpcode(Mips::LUi);
tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg())); tmpInst.addOperand(MCOperand::CreateReg(Reg));
tmpInst.addOperand( tmpInst.addOperand(
MCOperand::CreateImm((ImmValue & (0xffffLL << 48)) >> 48)); MCOperand::CreateImm((ImmValue & (0xffffLL << 48)) >> 48));
Instructions.push_back(tmpInst); Instructions.push_back(tmpInst);
createShiftOr<32, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions); createShiftOr<32, false>(ImmValue, Reg, IDLoc, Instructions);
createShiftOr<16, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions); createShiftOr<16, true>(ImmValue, Reg, IDLoc, Instructions);
createShiftOr<0, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions); createShiftOr<0, true>(ImmValue, Reg, IDLoc, Instructions);
} }
return false; return false;
} }