RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2025-05-13 10:56:01 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

reduce indentation; NFCI

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@270007 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel 2016-05-19 00:33:07 +00:00
parent d6995c8dcf
commit c40c117dfc
1 changed files with 7 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -2430,15 +2430,13 @@ SDValue DAGCombiner::visitREM(SDNode *N) {
}
// fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
if (N1.getOpcode() == ISD::SHL) {
if (ConstantSDNode *SHC = getAsNonOpaqueConstant(N1.getOperand(0))) {
if (SHC->getAPIntValue().isPowerOf2()) {
SDValue Add =
DAG.getNode(ISD::ADD, DL, VT, N1,
DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL,
VT));
AddToWorklist(Add.getNode());
return DAG.getNode(ISD::AND, DL, VT, N0, Add);
}
ConstantSDNode *SHC = getAsNonOpaqueConstant(N1.getOperand(0));
if (SHC && SHC->getAPIntValue().isPowerOf2()) {
APInt NegOne = APInt::getAllOnesValue(VT.getSizeInBits());
SDValue Add =
DAG.getNode(ISD::ADD, DL, VT, N1, DAG.getConstant(NegOne, DL, VT));
AddToWorklist(Add.getNode());
return DAG.getNode(ISD::AND, DL, VT, N0, Add);
}
}
}