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[AArch64] Add support for NEON scalar extract narrow instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192970 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
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c439c205ba
@ -3292,6 +3292,22 @@ multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>
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[], NoItinerary>;
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}
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multiclass NeonI_Scalar2SameMisc_narrow_HSD_size<bit u, bits<5> opcode,
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string asmop> {
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def bh : NeonI_Scalar2SameMisc<u, 0b00, opcode,
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(outs FPR8:$Rd), (ins FPR16:$Rn),
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!strconcat(asmop, " $Rd, $Rn"),
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[], NoItinerary>;
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def hs : NeonI_Scalar2SameMisc<u, 0b01, opcode,
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(outs FPR16:$Rd), (ins FPR32:$Rn),
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!strconcat(asmop, " $Rd, $Rn"),
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[], NoItinerary>;
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def sd : NeonI_Scalar2SameMisc<u, 0b10, opcode,
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(outs FPR32:$Rd), (ins FPR64:$Rn),
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!strconcat(asmop, " $Rd, $Rn"),
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[], NoItinerary>;
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}
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multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
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string asmop> {
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@ -3366,6 +3382,20 @@ multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
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(INSTS FPR32:$Rn)>;
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}
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multiclass Neon_Scalar2SameMisc_narrow_HSD_size_patterns<
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SDPatternOperator opnode,
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Instruction INSTH,
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Instruction INSTS,
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Instruction INSTD> {
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def : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn))),
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(INSTH FPR16:$Rn)>;
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def : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn))),
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(INSTS FPR32:$Rn)>;
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def : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn))),
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(INSTD FPR64:$Rn)>;
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}
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multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
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SDPatternOperator opnode,
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Instruction INSTB,
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@ -3645,6 +3675,24 @@ defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
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USQADDbb, USQADDhh,
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USQADDss, USQADDdd>;
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// Scalar Signed Saturating Extract Unsigned Narrow
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defm SQXTUN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10010, "sqxtun">;
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defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnsu,
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SQXTUNbh, SQXTUNhs,
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SQXTUNsd>;
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// Scalar Signed Saturating Extract Narrow
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defm SQXTN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b0, 0b10100, "sqxtn">;
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defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovns,
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SQXTNbh, SQXTNhs,
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SQXTNsd>;
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// Scalar Unsigned Saturating Extract Narrow
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defm UQXTN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10100, "uqxtn">;
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defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnu,
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UQXTNbh, UQXTNhs,
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UQXTNsd>;
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// Scalar Reduce Pairwise
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multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,
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104
test/CodeGen/AArch64/neon-scalar-extract-narrow.ll
Normal file
104
test/CodeGen/AArch64/neon-scalar-extract-narrow.ll
Normal file
@ -0,0 +1,104 @@
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; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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define i8 @test_vqmovunh_s16(i16 %a) {
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; CHECK: test_vqmovunh_s16
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; CHECK: sqxtun {{b[0-9]+}}, {{h[0-9]+}}
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entry:
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%vqmovun.i = insertelement <1 x i16> undef, i16 %a, i32 0
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%vqmovun1.i = call <1 x i8> @llvm.arm.neon.vqmovnsu.v1i8(<1 x i16> %vqmovun.i)
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%0 = extractelement <1 x i8> %vqmovun1.i, i32 0
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ret i8 %0
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}
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define i16 @test_vqmovuns_s32(i32 %a) {
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; CHECK: test_vqmovuns_s32
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; CHECK: sqxtun {{h[0-9]+}}, {{s[0-9]+}}
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entry:
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%vqmovun.i = insertelement <1 x i32> undef, i32 %a, i32 0
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%vqmovun1.i = call <1 x i16> @llvm.arm.neon.vqmovnsu.v1i16(<1 x i32> %vqmovun.i)
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%0 = extractelement <1 x i16> %vqmovun1.i, i32 0
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ret i16 %0
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}
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define i32 @test_vqmovund_s64(i64 %a) {
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; CHECK: test_vqmovund_s64
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; CHECK: sqxtun {{s[0-9]+}}, {{d[0-9]+}}
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entry:
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%vqmovun.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vqmovun1.i = call <1 x i32> @llvm.arm.neon.vqmovnsu.v1i32(<1 x i64> %vqmovun.i)
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%0 = extractelement <1 x i32> %vqmovun1.i, i32 0
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ret i32 %0
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}
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declare <1 x i8> @llvm.arm.neon.vqmovnsu.v1i8(<1 x i16>)
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declare <1 x i16> @llvm.arm.neon.vqmovnsu.v1i16(<1 x i32>)
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declare <1 x i32> @llvm.arm.neon.vqmovnsu.v1i32(<1 x i64>)
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define i8 @test_vqmovnh_s16(i16 %a) {
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; CHECK: test_vqmovnh_s16
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; CHECK: sqxtn {{b[0-9]+}}, {{h[0-9]+}}
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entry:
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%vqmovn.i = insertelement <1 x i16> undef, i16 %a, i32 0
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%vqmovn1.i = call <1 x i8> @llvm.arm.neon.vqmovns.v1i8(<1 x i16> %vqmovn.i)
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%0 = extractelement <1 x i8> %vqmovn1.i, i32 0
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ret i8 %0
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}
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define i16 @test_vqmovns_s32(i32 %a) {
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; CHECK: test_vqmovns_s32
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; CHECK: sqxtn {{h[0-9]+}}, {{s[0-9]+}}
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entry:
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%vqmovn.i = insertelement <1 x i32> undef, i32 %a, i32 0
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%vqmovn1.i = call <1 x i16> @llvm.arm.neon.vqmovns.v1i16(<1 x i32> %vqmovn.i)
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%0 = extractelement <1 x i16> %vqmovn1.i, i32 0
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ret i16 %0
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}
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define i32 @test_vqmovnd_s64(i64 %a) {
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; CHECK: test_vqmovnd_s64
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; CHECK: sqxtn {{s[0-9]+}}, {{d[0-9]+}}
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entry:
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%vqmovn.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vqmovn1.i = call <1 x i32> @llvm.arm.neon.vqmovns.v1i32(<1 x i64> %vqmovn.i)
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%0 = extractelement <1 x i32> %vqmovn1.i, i32 0
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ret i32 %0
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}
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declare <1 x i8> @llvm.arm.neon.vqmovns.v1i8(<1 x i16>)
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declare <1 x i16> @llvm.arm.neon.vqmovns.v1i16(<1 x i32>)
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declare <1 x i32> @llvm.arm.neon.vqmovns.v1i32(<1 x i64>)
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define i8 @test_vqmovnh_u16(i16 %a) {
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; CHECK: test_vqmovnh_u16
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; CHECK: uqxtn {{b[0-9]+}}, {{h[0-9]+}}
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entry:
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%vqmovn.i = insertelement <1 x i16> undef, i16 %a, i32 0
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%vqmovn1.i = call <1 x i8> @llvm.arm.neon.vqmovnu.v1i8(<1 x i16> %vqmovn.i)
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%0 = extractelement <1 x i8> %vqmovn1.i, i32 0
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ret i8 %0
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}
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define i16 @test_vqmovns_u32(i32 %a) {
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; CHECK: test_vqmovns_u32
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; CHECK: uqxtn {{h[0-9]+}}, {{s[0-9]+}}
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entry:
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%vqmovn.i = insertelement <1 x i32> undef, i32 %a, i32 0
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%vqmovn1.i = call <1 x i16> @llvm.arm.neon.vqmovnu.v1i16(<1 x i32> %vqmovn.i)
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%0 = extractelement <1 x i16> %vqmovn1.i, i32 0
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ret i16 %0
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}
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define i32 @test_vqmovnd_u64(i64 %a) {
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; CHECK: test_vqmovnd_u64
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; CHECK: uqxtn {{s[0-9]+}}, {{d[0-9]+}}
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entry:
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%vqmovn.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vqmovn1.i = call <1 x i32> @llvm.arm.neon.vqmovnu.v1i32(<1 x i64> %vqmovn.i)
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%0 = extractelement <1 x i32> %vqmovn1.i, i32 0
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ret i32 %0
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}
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declare <1 x i8> @llvm.arm.neon.vqmovnu.v1i8(<1 x i16>)
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declare <1 x i16> @llvm.arm.neon.vqmovnu.v1i16(<1 x i32>)
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declare <1 x i32> @llvm.arm.neon.vqmovnu.v1i32(<1 x i64>)
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@ -4502,3 +4502,58 @@
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqdmull d15, s22, d12
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// CHECK-ERROR: ^
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//----------------------------------------------------------------------
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// Scalar Signed Saturating Extract Unsigned Narrow
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//----------------------------------------------------------------------
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sqxtun b19, b14
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sqxtun h21, h15
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sqxtun s20, s12
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqxtun b19, b14
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqxtun h21, h15
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqxtun s20, s12
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// CHECK-ERROR: ^
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//----------------------------------------------------------------------
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// Scalar Signed Saturating Extract Signed Narrow
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//----------------------------------------------------------------------
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sqxtn b18, b18
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sqxtn h20, h17
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sqxtn s19, s14
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqxtn b18, b18
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqxtn h20, h17
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqxtn s19, s14
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// CHECK-ERROR: ^
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//----------------------------------------------------------------------
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// Scalar Unsigned Saturating Extract Narrow
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//----------------------------------------------------------------------
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uqxtn b18, b18
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uqxtn h20, h17
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uqxtn s19, s14
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: uqxtn b18, b18
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: uqxtn h20, h17
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: uqxtn s19, s14
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// CHECK-ERROR: ^
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40
test/MC/AArch64/neon-scalar-extract-narrow.s
Normal file
40
test/MC/AArch64/neon-scalar-extract-narrow.s
Normal file
@ -0,0 +1,40 @@
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// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
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// Check that the assembler can handle the documented syntax for AArch64
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//----------------------------------------------------------------------
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// Scalar Signed Saturating Extract Unsigned Narrow
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//----------------------------------------------------------------------
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sqxtun b19, h14
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sqxtun h21, s15
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sqxtun s20, d12
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// CHECK: sqxtun b19, h14 // encoding: [0xd3,0x29,0x21,0x7e]
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// CHECK: sqxtun h21, s15 // encoding: [0xf5,0x29,0x61,0x7e]
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// CHECK: sqxtun s20, d12 // encoding: [0x94,0x29,0xa1,0x7e]
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//----------------------------------------------------------------------
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// Scalar Signed Saturating Extract Signed Narrow
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//----------------------------------------------------------------------
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sqxtn b18, h18
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sqxtn h20, s17
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sqxtn s19, d14
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// CHECK: sqxtn b18, h18 // encoding: [0x52,0x4a,0x21,0x5e]
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// CHECK: sqxtn h20, s17 // encoding: [0x34,0x4a,0x61,0x5e]
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// CHECK: sqxtn s19, d14 // encoding: [0xd3,0x49,0xa1,0x5e]
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//----------------------------------------------------------------------
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// Scalar Unsigned Saturating Extract Narrow
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//----------------------------------------------------------------------
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uqxtn b18, h18
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uqxtn h20, s17
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uqxtn s19, d14
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// CHECK: uqxtn b18, h18 // encoding: [0x52,0x4a,0x21,0x7e]
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// CHECK: uqxtn h20, s17 // encoding: [0x34,0x4a,0x61,0x7e]
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// CHECK: uqxtn s19, d14 // encoding: [0xd3,0x49,0xa1,0x7e]
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@ -1683,3 +1683,33 @@
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# CHECK: sqdmull d15, s22, s12
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0xcc,0xd2,0x6c,0x5e
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0xcf,0xd2,0xac,0x5e
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#----------------------------------------------------------------------
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# Scalar Signed Saturating Extract Unsigned Narrow
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#----------------------------------------------------------------------
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# CHECK: sqxtun b19, h14
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# CHECK: sqxtun h21, s15
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# CHECK: sqxtun s20, d12
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0xd3,0x29,0x21,0x7e
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0xf5,0x29,0x61,0x7e
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0x94,0x29,0xa1,0x7e
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#----------------------------------------------------------------------
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# Scalar Signed Saturating Extract Signed Narrow
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#----------------------------------------------------------------------
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# CHECK: sqxtn b18, h18
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# CHECK: sqxtn h20, s17
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# CHECK: sqxtn s19, d14
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0x52,0x4a,0x21,0x5e
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0x34,0x4a,0x61,0x5e
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0xd3,0x49,0xa1,0x5e
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#----------------------------------------------------------------------
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# Scalar Unsigned Saturating Extract Narrow
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#----------------------------------------------------------------------
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# CHECK: uqxtn b18, h18
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# CHECK: uqxtn h20, s17
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# CHECK: uqxtn s19, d14
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0x52,0x4a,0x21,0x7e
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0x34,0x4a,0x61,0x7e
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0xd3,0x49,0xa1,0x7e
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