diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 8bdc8e37904..f2bf9172012 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -854,7 +854,7 @@ void LiveIntervals::shrinkToUses(LiveInterval *li,
       assert(MI && "No instruction defining live value");
       MI->addRegisterDead(li->reg, tri_);
       if (dead && MI->allDefsAreDead()) {
-        DEBUG(dbgs() << "All defs dead: " << *MI);
+        DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
         dead->push_back(MI);
       }
     }
@@ -862,7 +862,7 @@ void LiveIntervals::shrinkToUses(LiveInterval *li,
 
   // Move the trimmed ranges back.
   li->ranges.swap(NewLI.ranges);
-  DEBUG(dbgs() << "Shrink: " << *li << '\n');
+  DEBUG(dbgs() << "Shrunk: " << *li << '\n');
 }
 
 
diff --git a/lib/CodeGen/LiveRangeEdit.cpp b/lib/CodeGen/LiveRangeEdit.cpp
index c9985cd9d22..0769f95262d 100644
--- a/lib/CodeGen/LiveRangeEdit.cpp
+++ b/lib/CodeGen/LiveRangeEdit.cpp
@@ -148,17 +148,21 @@ void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
     while (!Dead.empty()) {
       MachineInstr *MI = Dead.pop_back_val();
       assert(MI->allDefsAreDead() && "Def isn't really dead");
+      SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
 
       // Never delete inline asm.
-      if (MI->isInlineAsm())
+      if (MI->isInlineAsm()) {
+        DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
         continue;
+      }
 
       // Use the same criteria as DeadMachineInstructionElim.
       bool SawStore = false;
-      if (!MI->isSafeToMove(&TII, 0, SawStore))
+      if (!MI->isSafeToMove(&TII, 0, SawStore)) {
+        DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
         continue;
+      }
 
-      SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
       DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
 
       // Check for live intervals that may shrink
diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp
index 57119aacd2b..940ed814652 100644
--- a/lib/CodeGen/RegAllocGreedy.cpp
+++ b/lib/CodeGen/RegAllocGreedy.cpp
@@ -646,7 +646,9 @@ void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, unsigned PhysReg,
     IndexPair &IP = InterferenceRanges[i];
     DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " -> EB#"
                  << Bundles->getBundle(BI.MBB->getNumber(), 1)
-                 << " intf [" << IP.first << ';' << IP.second << ')');
+                 << " [" << BI.Start << ';' << BI.LastSplitPoint << '-'
+                 << BI.Stop << ") intf [" << IP.first << ';' << IP.second
+                 << ')');
 
     // The interference interval should either be invalid or overlap MBB.
     assert((!IP.first.isValid() || IP.first < BI.Stop) && "Bad interference");
@@ -741,7 +743,8 @@ void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, unsigned PhysReg,
     IndexPair &IP = InterferenceRanges[i];
 
     DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0)
-                 << " -> BB#" << BI.MBB->getNumber());
+                 << " -> BB#" << BI.MBB->getNumber() << " [" << BI.Start << ';'
+                 << BI.LastSplitPoint << '-' << BI.Stop << ')');
 
     // Check interference entering the block.
     if (!IP.first.isValid()) {
@@ -1266,6 +1269,9 @@ unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
   LiveRangeEdit LRE(VirtReg, NewVRegs, this);
   spiller().spill(LRE);
 
+  if (VerifyEnabled)
+    MF->verify(this, "After spilling");
+
   // The live virtual register requesting allocation was spilled, so tell
   // the caller not to allocate anything during this round.
   return 0;