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Add instruction encodings / disassembly support for l4r instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2013-01-25 21:55:32 +00:00
parent c655c43ba5
commit c47bd9899b
4 changed files with 93 additions and 17 deletions
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49
lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
View File

@ -180,6 +180,16 @@ static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
#include "XCoreGenDisassemblerTables.inc"
static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
@ -636,6 +646,45 @@ DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
return S;
}
static DecodeStatus
DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3;
unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
}
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
}
return S;
}
static DecodeStatus
DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3;
unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
}
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
}
return S;
}
MCDisassembler::DecodeStatus
XCoreDisassembler::getInstruction(MCInst &instr,
uint64_t &Size,

23
lib/Target/XCore/XCoreInstrFormats.td
View File

@ -218,8 +218,29 @@ class _F0R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{4-0} = opc{4-0};
}
class _L4R<dag outs, dag ins, string asmstr, list<dag> pattern>
class _FL4R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
bits<4> d;
let Inst{31-27} = opc{5-1};
let Inst{26-21} = 0b111111;
let Inst{20} = opc{0};
let Inst{19-16} = d;
let Inst{15-11} = 0b11111;
}
// L4R with 4th operand as both a source and a destination.
class _FL4RSrcDst<bits<6> opc, dag outs, dag ins, string asmstr,
list<dag> pattern>
: _FL4R<opc, outs, ins, asmstr, pattern> {
let DecoderMethod = "DecodeL4RSrcDstInstruction";
}
// L4R with 1st and 4th operand as both a source and a destination.
class _FL4RSrcDstSrcDst<bits<6> opc, dag outs, dag ins, string asmstr,
list<dag> pattern>
: _FL4R<opc, outs, ins, asmstr, pattern> {
let DecoderMethod = "DecodeL4RSrcDstSrcDstInstruction";
}
class _FL5R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>

27
lib/Target/XCore/XCoreInstrInfo.td
View File

@ -463,25 +463,20 @@ def ST8_l3r : _FL3R<0b100011100, (outs),
}
// Four operand long
let Constraints = "$src1 = $dst1,$src2 = $dst2" in {
def MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
GRRegs:$src4),
"maccu $dst1, $dst2, $src3, $src4",
[]>;
let Constraints = "$e = $a,$f = $b" in {
def MACCU_l4r : _FL4RSrcDstSrcDst<
0b000001, (outs GRRegs:$a, GRRegs:$b),
(ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccu $a, $b, $c, $d", []>;
def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
GRRegs:$src4),
"maccs $dst1, $dst2, $src3, $src4",
[]>;
def MACCS_l4r : _FL4RSrcDstSrcDst<
0b000010, (outs GRRegs:$a, GRRegs:$b),
(ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccs $a, $b, $c, $d", []>;
}
let Constraints = "$src1 = $dst2" in
def CRC8_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
"crc8 $dst2, $dst1, $src2, $src3",
[]>;
let Constraints = "$e = $b" in
def CRC8_l4r : _FL4RSrcDst<0b000000, (outs GRRegs:$a, GRRegs:$b),
(ins GRRegs:$e, GRRegs:$c, GRRegs:$d),
"crc8 $b, $a, $c, $d", []>;
// Five operand long

11
test/MC/Disassembler/XCore/xcore.txt
View File

@ -472,3 +472,14 @@
# CHECK: lsub r1, r8, r7, r11, r5
0xcf 0xfd 0x85 0x0f
# l4r instructions
# CHECK: crc8 r6, r3, r4, r11
0x73 0xfd 0xe6 0x07
# CHECK: maccs r11, r8, r2, r4
0xf8 0xfa 0xe8 0x0f
# CHECK: maccu r0, r2, r5, r8
0x44 0xfd 0xf2 0x07