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Limit the range of processors supported by ARM fast isel to v6 or

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later as that's all that is tested right now.

Fixes PR24858.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248027 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2015-09-18 20:08:18 +00:00
parent c4736349a5
commit c4db514911
3 changed files with 4 additions and 36 deletions
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4
lib/Target/ARM/ARMSubtarget.cpp
View File

@ -298,6 +298,10 @@ bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
}
bool ARMSubtarget::useFastISel() const {
// Limit fast-isel to the targets that are or have been tested.
if (!hasV6Ops())
return false;
// Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
return TM.Options.EnableFastISel &&
((isTargetMachO() && !isThumb1Only()) ||

35
test/CodeGen/ARM/fast-isel-ext.ll
View File

@ -1,9 +1,5 @@
; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7
; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=v7
; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv4t-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6
; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv4t-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6
; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv5-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6
; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv5-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6
; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7
; Can't test pre-ARMv6 Thumb because ARM FastISel currently only supports
@ -19,8 +15,6 @@
define i8 @zext_1_8(i1 %a) nounwind ssp {
; v7-LABEL: zext_1_8:
; v7: and r0, r0, #1
; prev6-LABEL: zext_1_8:
; prev6: and r0, r0, #1
%r = zext i1 %a to i8
ret i8 %r
}
@ -28,8 +22,6 @@ define i8 @zext_1_8(i1 %a) nounwind ssp {
define i16 @zext_1_16(i1 %a) nounwind ssp {
; v7-LABEL: zext_1_16:
; v7: and r0, r0, #1
; prev6-LABEL: zext_1_16:
; prev6: and r0, r0, #1
%r = zext i1 %a to i16
ret i16 %r
}
@ -37,8 +29,6 @@ define i16 @zext_1_16(i1 %a) nounwind ssp {
define i32 @zext_1_32(i1 %a) nounwind ssp {
; v7-LABEL: zext_1_32:
; v7: and r0, r0, #1
; prev6-LABEL: zext_1_32:
; prev6: and r0, r0, #1
%r = zext i1 %a to i32
ret i32 %r
}
@ -46,8 +36,6 @@ define i32 @zext_1_32(i1 %a) nounwind ssp {
define i16 @zext_8_16(i8 %a) nounwind ssp {
; v7-LABEL: zext_8_16:
; v7: and r0, r0, #255
; prev6-LABEL: zext_8_16:
; prev6: and r0, r0, #255
%r = zext i8 %a to i16
ret i16 %r
}
@ -55,8 +43,6 @@ define i16 @zext_8_16(i8 %a) nounwind ssp {
define i32 @zext_8_32(i8 %a) nounwind ssp {
; v7-LABEL: zext_8_32:
; v7: and r0, r0, #255
; prev6-LABEL: zext_8_32:
; prev6: and r0, r0, #255
%r = zext i8 %a to i32
ret i32 %r
}
@ -64,9 +50,6 @@ define i32 @zext_8_32(i8 %a) nounwind ssp {
define i32 @zext_16_32(i16 %a) nounwind ssp {
; v7-LABEL: zext_16_32:
; v7: uxth r0, r0
; prev6-LABEL: zext_16_32:
; prev6: lsl{{s?}} r0, r0, #16
; prev6: lsr{{s?}} r0, r0, #16
%r = zext i16 %a to i32
ret i32 %r
}
@ -77,9 +60,6 @@ define i8 @sext_1_8(i1 %a) nounwind ssp {
; v7-LABEL: sext_1_8:
; v7: lsl{{s?}} r0, r0, #31
; v7: asr{{s?}} r0, r0, #31
; prev6-LABEL: sext_1_8:
; prev6: lsl{{s?}} r0, r0, #31
; prev6: asr{{s?}} r0, r0, #31
%r = sext i1 %a to i8
ret i8 %r
}
@ -88,9 +68,6 @@ define i16 @sext_1_16(i1 %a) nounwind ssp {
; v7-LABEL: sext_1_16:
; v7: lsl{{s?}} r0, r0, #31
; v7: asr{{s?}} r0, r0, #31
; prev6-LABEL: sext_1_16:
; prev6: lsl{{s?}} r0, r0, #31
; prev6: asr{{s?}} r0, r0, #31
%r = sext i1 %a to i16
ret i16 %r
}
@ -99,9 +76,6 @@ define i32 @sext_1_32(i1 %a) nounwind ssp {
; v7-LABEL: sext_1_32:
; v7: lsl{{s?}} r0, r0, #31
; v7: asr{{s?}} r0, r0, #31
; prev6-LABEL: sext_1_32:
; prev6: lsl{{s?}} r0, r0, #31
; prev6: asr{{s?}} r0, r0, #31
%r = sext i1 %a to i32
ret i32 %r
}
@ -109,9 +83,6 @@ define i32 @sext_1_32(i1 %a) nounwind ssp {
define i16 @sext_8_16(i8 %a) nounwind ssp {
; v7-LABEL: sext_8_16:
; v7: sxtb r0, r0
; prev6-LABEL: sext_8_16:
; prev6: lsl{{s?}} r0, r0, #24
; prev6: asr{{s?}} r0, r0, #24
%r = sext i8 %a to i16
ret i16 %r
}
@ -119,9 +90,6 @@ define i16 @sext_8_16(i8 %a) nounwind ssp {
define i32 @sext_8_32(i8 %a) nounwind ssp {
; v7-LABEL: sext_8_32:
; v7: sxtb r0, r0
; prev6-LABEL: sext_8_32:
; prev6: lsl{{s?}} r0, r0, #24
; prev6: asr{{s?}} r0, r0, #24
%r = sext i8 %a to i32
ret i32 %r
}
@ -129,9 +97,6 @@ define i32 @sext_8_32(i8 %a) nounwind ssp {
define i32 @sext_16_32(i16 %a) nounwind ssp {
; v7-LABEL: sext_16_32:
; v7: sxth r0, r0
; prev6-LABEL: sext_16_32:
; prev6: lsl{{s?}} r0, r0, #16
; prev6: asr{{s?}} r0, r0, #16
%r = sext i16 %a to i32
ret i32 %r
}

1
test/CodeGen/ARM/fast-isel-pic.ll
View File

@ -1,5 +1,4 @@
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF