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All addressing modes are now exposed. The only remaining relocated forms
are for function prologue. TODO: move external symbols over to using RelLit. : have a pattern that matches constpool|globaladdr : have a pattern that matches (add x imm) -> x, imm or (...) -> ..., 0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25003 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -212,12 +212,6 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
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Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg());
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return CurDAG->SelectNodeTo(N, Alpha::LDAr, MVT::i64, CPI, Tmp);
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}
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case ISD::TargetGlobalAddress: {
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GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
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SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
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return CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64, GA,
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getGlobalBaseReg());
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}
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case ISD::ExternalSymbol:
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return CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64,
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CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(), MVT::i64),
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@ -459,7 +459,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
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return Lo;
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} else
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return GA;
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return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
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}
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}
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@ -29,12 +29,11 @@ namespace llvm {
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ITOFT_, FTOIT_, CVTQT_, CVTQS_, CVTTQ_,
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/// GPRelHi/GPRelLo - These represent the high and low 16-bit
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/// parts of a global address respectively. These nodes have
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/// two operands, the first of which must be a
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/// TargetGlobalAddress, and the second of which must be a
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/// Constant. Selected naively, these turn into 'ldah R(G)' and
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/// 'lda R(C)', though these are usually folded into other nodes.
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GPRelHi, GPRelLo,
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/// parts of a global address respectively.
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GPRelHi, GPRelLo,
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/// RetLit - Literal Relocation of a Global
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RelLit,
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/// GlobalBaseReg, used to restore the GOT ptr
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GlobalBaseReg,
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@ -744,20 +744,13 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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else assert(0 && "unknown Lo part");
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return Result;
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case ISD::GlobalAddress:
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AlphaLowering.restoreGP(BB);
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has_sym = true;
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Reg = Result = MakeReg(MVT::i64);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
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.addImm(getUID());
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case AlphaISD::RelLit: {
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GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N.getOperand(0));
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BuildMI(BB, Alpha::LDQl, 2, Result)
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.addGlobalAddress(cast<GlobalAddressSDNode>(N)->getGlobal())
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.addReg(Alpha::R29);
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.addGlobalAddress(GASD->getGlobal())
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.addReg(SelectExpr(N.getOperand(1)));
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return Result;
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}
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case ISD::ExternalSymbol:
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AlphaLowering.restoreGP(BB);
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@ -27,6 +27,7 @@ def Alpha_cvtqs : SDNode<"AlphaISD::CVTQS_", SDTFPUnaryOpUnC, []>;
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def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_", SDTFPUnaryOp, []>;
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def Alpha_gprello : SDNode<"AlphaISD::GPRelLo", SDTIntBinOp, []>;
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def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi", SDTIntBinOp, []>;
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def Alpha_rellit : SDNode<"AlphaISD::RelLit", SDTIntBinOp, []>;
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// These are target-independent nodes, but have target-specific formats.
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def SDT_AlphaCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i64> ]>;
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@ -505,6 +506,26 @@ def LDTr : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)\t\t!gprellow",
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[(set F8RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))]>;
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}
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//constpool rels
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def : Pat<(i64 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
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(LDQr tconstpool:$DISP, GPRC:$RB)>;
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def : Pat<(i64 (sextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i32)),
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(LDLr tconstpool:$DISP, GPRC:$RB)>;
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def : Pat<(i64 (zextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i8)),
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(LDBUr tconstpool:$DISP, GPRC:$RB)>;
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def : Pat<(i64 (zextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i16)),
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(LDWUr tconstpool:$DISP, GPRC:$RB)>;
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def : Pat<(i64 (Alpha_gprello tconstpool:$DISP, GPRC:$RB)),
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(LDAr tconstpool:$DISP, GPRC:$RB)>;
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def : Pat<(i64 (Alpha_gprelhi tconstpool:$DISP, GPRC:$RB)),
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(LDAHr tconstpool:$DISP, GPRC:$RB)>;
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def : Pat<(f32 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
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(LDSr tconstpool:$DISP, GPRC:$RB)>;
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def : Pat<(f64 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
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(LDTr tconstpool:$DISP, GPRC:$RB)>;
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//misc ext patterns
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def : Pat<(i64 (extload (add GPRC:$RB, immSExt16:$DISP), i8)),
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(LDBU immSExt16:$DISP, GPRC:$RB)>;
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@ -533,6 +554,19 @@ def : Pat<(i64 (extload GPRC:$addr, i16)),
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def : Pat<(i64 (extload GPRC:$addr, i32)),
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(LDL 0, GPRC:$addr)>;
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def : Pat<(store GPRC:$DATA, GPRC:$addr),
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(STQ GPRC:$DATA, 0, GPRC:$addr)>;
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def : Pat<(store F8RC:$DATA, GPRC:$addr),
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(STT F8RC:$DATA, 0, GPRC:$addr)>;
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def : Pat<(store F4RC:$DATA, GPRC:$addr),
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(STS F4RC:$DATA, 0, GPRC:$addr)>;
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def : Pat<(truncstore GPRC:$DATA, GPRC:$addr, i32),
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(STL GPRC:$DATA, 0, GPRC:$addr)>;
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def : Pat<(truncstore GPRC:$DATA, GPRC:$addr, i16),
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(STW GPRC:$DATA, 0, GPRC:$addr)>;
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def : Pat<(truncstore GPRC:$DATA, GPRC:$addr, i8),
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(STB GPRC:$DATA, 0, GPRC:$addr)>;
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//load address, rellocated gpdist form
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let OperandList = (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in {
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@ -541,8 +575,9 @@ def LDAHg : MFormAlt<0x09, "ldah $RA,0($RB)\t\t!gpdisp!$NUM">; //Load address
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}
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//Load quad, rellocated literal form
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let isLoad = 1, OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in
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def LDQl : MFormAlt<0x29, "ldq $RA,$DISP($RB)\t\t!literal">; //Load quadword
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let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in
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def LDQl : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!literal",
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[(set GPRC:$RA, (Alpha_rellit tglobaladdr:$DISP, GPRC:$RB))]>;
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//Branches, int
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def BEQ : BForm<0x39, "beq $RA,$DISP">; //Branch if = zero
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