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De-virtualize or remove some methods that have no overrides nor override anything. In some cases remove all together if there are no callers either.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207610 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2014-04-30 05:53:27 +00:00
parent 38bd5c4bf9
commit c6b0620101
7 changed files with 7 additions and 27 deletions
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13
lib/Target/NVPTX/NVPTXRegisterInfo.cpp
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@ -84,13 +84,6 @@ NVPTXRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
return CalleeSavedRegs;
}
// NVPTX Callee Saved Reg Classes
const TargetRegisterClass *const *
NVPTXRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
static const TargetRegisterClass *const CalleeSavedRegClasses[] = { nullptr };
return CalleeSavedRegClasses;
}
BitVector NVPTXRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
return Reserved;
@ -113,12 +106,6 @@ void NVPTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
}
int NVPTXRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
return 0;
}
unsigned NVPTXRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
return NVPTX::VRFrame;
}
unsigned NVPTXRegisterInfo::getRARegister() const { return 0; }

6
lib/Target/NVPTX/NVPTXRegisterInfo.h
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@ -44,19 +44,13 @@ public:
const MCPhysReg *
getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
// NVPTX callee saved register classes
virtual const TargetRegisterClass *const *
getCalleeSavedRegClasses(const MachineFunction *MF) const final;
BitVector getReservedRegs(const MachineFunction &MF) const override;
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
unsigned FIOperandNum,
RegScavenger *RS = nullptr) const override;
virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const final;
unsigned getFrameRegister(const MachineFunction &MF) const override;
virtual unsigned getRARegister() const final;
ManagedStringPool *getStrPool() const {
return const_cast<ManagedStringPool *>(&ManagedStrPool);

2
lib/Target/PowerPC/PPCInstrInfo.h
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@ -227,7 +227,7 @@ public:
/// GetInstSize - Return the number of bytes of code the specified
/// instruction may be. This returns the maximum number of bytes.
///
virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const final;
unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
};
}

2
lib/Target/R600/AMDGPUFrameLowering.h
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@ -33,7 +33,7 @@ public:
/// \returns The number of 32-bit sub-registers that are used when storing
/// values to the stack.
virtual unsigned getStackWidth(const MachineFunction &MF) const final;
unsigned getStackWidth(const MachineFunction &MF) const;
int getFrameIndexOffset(const MachineFunction &MF, int FI) const override;
const SpillSlot *
getCalleeSavedSpillSlots(unsigned &NumEntries) const override;

7
lib/Target/R600/AMDGPUInstrInfo.h
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@ -103,11 +103,11 @@ protected:
MachineInstr *LoadMI) const override;
/// \returns the smallest register index that will be accessed by an indirect
/// read or write or -1 if indirect addressing is not used by this program.
virtual int getIndirectIndexBegin(const MachineFunction &MF) const final;
int getIndirectIndexBegin(const MachineFunction &MF) const;
/// \returns the largest register index that will be accessed by an indirect
/// read or write or -1 if indirect addressing is not used by this program.
virtual int getIndirectIndexEnd(const MachineFunction &MF) const final;
int getIndirectIndexEnd(const MachineFunction &MF) const;
public:
bool canFoldMemoryOperand(const MachineInstr *MI,
@ -188,8 +188,7 @@ public:
/// \brief Convert the AMDIL MachineInstr to a supported ISA
/// MachineInstr
virtual void convertToISA(MachineInstr & MI, MachineFunction &MF,
DebugLoc DL) const final;
void convertToISA(MachineInstr & MI, MachineFunction &MF, DebugLoc DL) const;
/// \brief Build a MOV instruction.
virtual MachineInstr *buildMovInstr(MachineBasicBlock *MBB,

2
lib/Target/R600/AMDGPUSubtarget.h
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@ -60,7 +60,7 @@ public:
AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS);
const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
virtual void ParseSubtargetFeatures(StringRef CPU, StringRef FS) final;
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool is64bit() const;
bool hasVertexCache() const;

2
lib/Target/R600/R600RegisterInfo.h
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@ -49,7 +49,7 @@ struct R600RegisterInfo : public AMDGPURegisterInfo {
getRegClassWeight(const TargetRegisterClass *RC) const override;
// \returns true if \p Reg can be defined in one ALU caluse and used in another.
virtual bool isPhysRegLiveAcrossClauses(unsigned Reg) const final;
bool isPhysRegLiveAcrossClauses(unsigned Reg) const;
};
} // End namespace llvm