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[mips][micromips] Initial support for micrmomips DSP instructions and addu.qb implementation

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Differential Revision: http://reviews.llvm.org/D12798


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250058 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic 2015-10-12 16:07:25 +00:00
parent 0b63e20666
commit c6d9c4ee81
12 changed files with 94 additions and 6 deletions
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1
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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@ -483,6 +483,7 @@ public:
bool hasDSP() const { return STI.getFeatureBits()[Mips::FeatureDSP]; }
bool hasDSPR2() const { return STI.getFeatureBits()[Mips::FeatureDSPR2]; }
bool hasDSPR3() const { return STI.getFeatureBits()[Mips::FeatureDSPR3]; }
bool hasMSA() const { return STI.getFeatureBits()[Mips::FeatureMSA]; }
bool hasCnMips() const {
return (STI.getFeatureBits()[Mips::FeatureCnMips]);

4
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
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@ -190,6 +190,10 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS,
else
NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
// Check whether it is Dsp instruction.
if (NewOpcode == -1)
NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp);
if (NewOpcode != -1) {
if (Fixups.size() > N)
Fixups.pop_back();

28
lib/Target/Mips/MicroMipsDSPInstrFormats.td Normal file
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@ -0,0 +1,28 @@
//===-- MicroMipsDSPInstrFormats.td - Instruction Formats --*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
class MMDSPInst<string opstr = "">
: MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
let InsnPredicates = [HasDSP];
string BaseOpcode = opstr;
string Arch = "mmdsp";
let DecoderNamespace = "MicroMips";
}
class POOL32A_3R_FMT<bits<11> op> : MMDSPInst {
bits<5> rd;
bits<5> rs;
bits<5> rt;
let Inst{31-26} = 0b000000;
let Inst{25-21} = rt;
let Inst{20-16} = rs;
let Inst{15-11} = rd;
let Inst{10-0} = op;
}

19
lib/Target/Mips/MicroMipsDSPInstrInfo.td Normal file
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@ -0,0 +1,19 @@
//===- MicroMipsDSPInstrInfo.td - Micromips DSP instructions -*- tablegen *-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes MicroMips DSP instructions.
//
//===----------------------------------------------------------------------===//
// Instruction encoding.
class ADDU_QB_MM_ENC : POOL32A_3R_FMT<0b00011001101>;
// Instruction defs.
// MIPS DSP Rev 1
def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC, ISA_MICROMIPS;

3
lib/Target/Mips/Mips.td
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@ -154,6 +154,9 @@ def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
"Mips DSP-R2 ASE", [FeatureDSP]>;
def FeatureDSPR3
: SubtargetFeature<"dspr3", "HasDSPR3", "true", "Mips DSP-R3 ASE",
[ FeatureDSP, FeatureDSPR2 ]>;
def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;

21
lib/Target/Mips/MipsDSPInstrFormats.td
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@ -7,10 +7,26 @@
//
//===----------------------------------------------------------------------===//
class DspMMRel;
def Dsp2MicroMips : InstrMapping {
let FilterClass = "DspMMRel";
// Instructions with the same BaseOpcode and isNVStore values form a row.
let RowFields = ["BaseOpcode"];
// Instructions with the same predicate sense form a column.
let ColFields = ["Arch"];
// The key column is the unpredicated instructions.
let KeyCol = ["dsp"];
// Value columns are PredSense=true and PredSense=false
let ValueCols = [["dsp"], ["mmdsp"]];
}
def HasDSP : Predicate<"Subtarget->hasDSP()">,
AssemblerPredicate<"FeatureDSP">;
def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">,
AssemblerPredicate<"FeatureDSPR2">;
def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">,
AssemblerPredicate<"FeatureDSPR3">;
// Fields.
class Field6<bits<6> val> {
@ -20,8 +36,11 @@ class Field6<bits<6> val> {
def SPECIAL3_OPCODE : Field6<0b011111>;
def REGIMM_OPCODE : Field6<0b000001>;
class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
class DSPInst<string opstr = "">
: MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
let Predicates = [HasDSP];
string BaseOpcode = opstr;
string Arch = "dsp";
}
class PseudoDSP<dag outs, dag ins, list<dag> pattern,

2
lib/Target/Mips/MipsDSPInstrInfo.td
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@ -1072,7 +1072,7 @@ def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
// Instruction defs.
// MIPS DSP Rev 1
def ADDU_QB : ADDU_QB_ENC, ADDU_QB_DESC;
def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC;
def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;

4
lib/Target/Mips/MipsInstrInfo.td
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@ -2109,3 +2109,7 @@ include "MicroMips32r6InstrInfo.td"
// Micromips64 r6
include "MicroMips64r6InstrFormats.td"
include "MicroMips64r6InstrInfo.td"
// Micromips DSP
include "MicroMipsDSPInstrFormats.td"
include "MicroMipsDSPInstrInfo.td"

4
lib/Target/Mips/MipsSubtarget.cpp
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@ -69,8 +69,8 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU,
HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
HasMSA(false), UseTCCInDIV(false), HasEVA(false), TM(TM),
HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasEVA(false), TM(TM),
TargetTriple(TT), TSInfo(),
InstrInfo(
MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),

5
lib/Target/Mips/MipsSubtarget.h
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@ -122,8 +122,8 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
// InMicroMips -- can process MicroMips instructions
bool InMicroMipsMode;
// HasDSP, HasDSPR2 -- supports DSP ASE.
bool HasDSP, HasDSPR2;
// HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
bool HasDSP, HasDSPR2, HasDSPR3;
// Allow mixed Mips16 and Mips32 in one source file
bool AllowMixed16_32;
@ -243,6 +243,7 @@ public:
bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); }
bool hasDSP() const { return HasDSP; }
bool hasDSPR2() const { return HasDSPR2; }
bool hasDSPR3() const { return HasDSPR3; }
bool hasMSA() const { return HasMSA; }
bool hasEVA() const { return HasEVA; }
bool useSmallSection() const { return UseSmallSection; }

4
test/MC/Disassembler/Mips/micromips-dsp/valid.txt Normal file
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@ -0,0 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips -mattr=+dsp | FileCheck %s
0x00 0xa4 0x18 0xcd # CHECK: addu.qb $3, $4, $5

5
test/MC/Mips/micromips-dsp/valid.s Normal file
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@ -0,0 +1,5 @@
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dsp | FileCheck %s
.set noat
addu.qb $3, $4, $5 # CHECK: addu.qb $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xcd]