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[mips][micromips] Initial support for micrmomips DSP instructions and addu.qb implementation
Differential Revision: http://reviews.llvm.org/D12798 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250058 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -483,6 +483,7 @@ public:
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bool hasDSP() const { return STI.getFeatureBits()[Mips::FeatureDSP]; }
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bool hasDSP() const { return STI.getFeatureBits()[Mips::FeatureDSP]; }
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bool hasDSPR2() const { return STI.getFeatureBits()[Mips::FeatureDSPR2]; }
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bool hasDSPR2() const { return STI.getFeatureBits()[Mips::FeatureDSPR2]; }
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bool hasDSPR3() const { return STI.getFeatureBits()[Mips::FeatureDSPR3]; }
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bool hasMSA() const { return STI.getFeatureBits()[Mips::FeatureMSA]; }
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bool hasMSA() const { return STI.getFeatureBits()[Mips::FeatureMSA]; }
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bool hasCnMips() const {
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bool hasCnMips() const {
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return (STI.getFeatureBits()[Mips::FeatureCnMips]);
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return (STI.getFeatureBits()[Mips::FeatureCnMips]);
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@ -190,6 +190,10 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS,
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else
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else
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NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
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NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
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// Check whether it is Dsp instruction.
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if (NewOpcode == -1)
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NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp);
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if (NewOpcode != -1) {
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if (NewOpcode != -1) {
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if (Fixups.size() > N)
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if (Fixups.size() > N)
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Fixups.pop_back();
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Fixups.pop_back();
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28
lib/Target/Mips/MicroMipsDSPInstrFormats.td
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28
lib/Target/Mips/MicroMipsDSPInstrFormats.td
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@ -0,0 +1,28 @@
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//===-- MicroMipsDSPInstrFormats.td - Instruction Formats --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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class MMDSPInst<string opstr = "">
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: MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
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let InsnPredicates = [HasDSP];
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string BaseOpcode = opstr;
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string Arch = "mmdsp";
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let DecoderNamespace = "MicroMips";
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}
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class POOL32A_3R_FMT<bits<11> op> : MMDSPInst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-11} = rd;
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let Inst{10-0} = op;
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}
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19
lib/Target/Mips/MicroMipsDSPInstrInfo.td
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19
lib/Target/Mips/MicroMipsDSPInstrInfo.td
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//===- MicroMipsDSPInstrInfo.td - Micromips DSP instructions -*- tablegen *-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes MicroMips DSP instructions.
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//
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//===----------------------------------------------------------------------===//
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// Instruction encoding.
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class ADDU_QB_MM_ENC : POOL32A_3R_FMT<0b00011001101>;
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// Instruction defs.
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// MIPS DSP Rev 1
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def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC, ISA_MICROMIPS;
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@ -154,6 +154,9 @@ def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
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def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
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def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
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def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
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def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
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"Mips DSP-R2 ASE", [FeatureDSP]>;
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"Mips DSP-R2 ASE", [FeatureDSP]>;
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def FeatureDSPR3
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: SubtargetFeature<"dspr3", "HasDSPR3", "true", "Mips DSP-R3 ASE",
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[ FeatureDSP, FeatureDSPR2 ]>;
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def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
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def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
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@ -7,10 +7,26 @@
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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class DspMMRel;
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def Dsp2MicroMips : InstrMapping {
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let FilterClass = "DspMMRel";
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// Instructions with the same BaseOpcode and isNVStore values form a row.
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let RowFields = ["BaseOpcode"];
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// Instructions with the same predicate sense form a column.
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let ColFields = ["Arch"];
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// The key column is the unpredicated instructions.
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let KeyCol = ["dsp"];
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// Value columns are PredSense=true and PredSense=false
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let ValueCols = [["dsp"], ["mmdsp"]];
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}
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def HasDSP : Predicate<"Subtarget->hasDSP()">,
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def HasDSP : Predicate<"Subtarget->hasDSP()">,
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AssemblerPredicate<"FeatureDSP">;
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AssemblerPredicate<"FeatureDSP">;
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def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">,
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def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">,
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AssemblerPredicate<"FeatureDSPR2">;
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AssemblerPredicate<"FeatureDSPR2">;
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def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">,
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AssemblerPredicate<"FeatureDSPR3">;
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// Fields.
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// Fields.
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class Field6<bits<6> val> {
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class Field6<bits<6> val> {
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@ -20,8 +36,11 @@ class Field6<bits<6> val> {
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def SPECIAL3_OPCODE : Field6<0b011111>;
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def SPECIAL3_OPCODE : Field6<0b011111>;
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def REGIMM_OPCODE : Field6<0b000001>;
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def REGIMM_OPCODE : Field6<0b000001>;
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class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
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class DSPInst<string opstr = "">
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: MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
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let Predicates = [HasDSP];
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let Predicates = [HasDSP];
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string BaseOpcode = opstr;
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string Arch = "dsp";
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}
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}
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class PseudoDSP<dag outs, dag ins, list<dag> pattern,
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class PseudoDSP<dag outs, dag ins, list<dag> pattern,
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@ -1072,7 +1072,7 @@ def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
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// Instruction defs.
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// Instruction defs.
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// MIPS DSP Rev 1
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// MIPS DSP Rev 1
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def ADDU_QB : ADDU_QB_ENC, ADDU_QB_DESC;
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def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
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def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC;
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def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC;
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def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
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def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
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def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
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def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
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@ -2109,3 +2109,7 @@ include "MicroMips32r6InstrInfo.td"
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// Micromips64 r6
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// Micromips64 r6
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include "MicroMips64r6InstrFormats.td"
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include "MicroMips64r6InstrFormats.td"
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include "MicroMips64r6InstrInfo.td"
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include "MicroMips64r6InstrInfo.td"
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// Micromips DSP
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include "MicroMipsDSPInstrFormats.td"
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include "MicroMipsDSPInstrInfo.td"
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@ -69,8 +69,8 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU,
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HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
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HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
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HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
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HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
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InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
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InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
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HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
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HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
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HasMSA(false), UseTCCInDIV(false), HasEVA(false), TM(TM),
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Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasEVA(false), TM(TM),
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TargetTriple(TT), TSInfo(),
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TargetTriple(TT), TSInfo(),
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InstrInfo(
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InstrInfo(
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MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
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MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
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@ -122,8 +122,8 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
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// InMicroMips -- can process MicroMips instructions
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// InMicroMips -- can process MicroMips instructions
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bool InMicroMipsMode;
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bool InMicroMipsMode;
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// HasDSP, HasDSPR2 -- supports DSP ASE.
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// HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
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bool HasDSP, HasDSPR2;
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bool HasDSP, HasDSPR2, HasDSPR3;
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// Allow mixed Mips16 and Mips32 in one source file
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// Allow mixed Mips16 and Mips32 in one source file
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bool AllowMixed16_32;
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bool AllowMixed16_32;
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@ -243,6 +243,7 @@ public:
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bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); }
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bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); }
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bool hasDSP() const { return HasDSP; }
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bool hasDSP() const { return HasDSP; }
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bool hasDSPR2() const { return HasDSPR2; }
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bool hasDSPR2() const { return HasDSPR2; }
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bool hasDSPR3() const { return HasDSPR3; }
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bool hasMSA() const { return HasMSA; }
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bool hasMSA() const { return HasMSA; }
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bool hasEVA() const { return HasEVA; }
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bool hasEVA() const { return HasEVA; }
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bool useSmallSection() const { return UseSmallSection; }
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bool useSmallSection() const { return UseSmallSection; }
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4
test/MC/Disassembler/Mips/micromips-dsp/valid.txt
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4
test/MC/Disassembler/Mips/micromips-dsp/valid.txt
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# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips -mattr=+dsp | FileCheck %s
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0x00 0xa4 0x18 0xcd # CHECK: addu.qb $3, $4, $5
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5
test/MC/Mips/micromips-dsp/valid.s
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5
test/MC/Mips/micromips-dsp/valid.s
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# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dsp | FileCheck %s
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.set noat
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addu.qb $3, $4, $5 # CHECK: addu.qb $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xcd]
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