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LiveIntervalAnalysis: Fix missing case in pruneSubRegValues()

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pruneSubRegValues() needs to remove subregister ranges starting at
instructions that later get removed by eraseInstrs(). It missed to check
one case in which eraseInstrs() would remove an instruction.

Fixes http://llvm.org/PR32688

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303396 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun 2017-05-19 00:18:03 +00:00
parent e5313997b5
commit c6f33b7e68
2 changed files with 38 additions and 1 deletions
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8
lib/CodeGen/RegisterCoalescer.cpp
View File

@ -2666,11 +2666,17 @@ void JoinVals::pruneSubRegValues(LiveInterval &LI, LaneBitmask &ShrinkMask) {
// Look for values being erased.
bool DidPrune = false;
for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
if (Vals[i].Resolution != CR_Erase)
// We should trigger in all cases in which eraseInstrs() does something.
// match what eraseInstrs() is doing, print a message so
if (Vals[i].Resolution != CR_Erase &&
(Vals[i].Resolution != CR_Keep || !Vals[i].ErasableImplicitDef ||
!Vals[i].Pruned))
continue;
// Check subranges at the point where the copy will be removed.
SlotIndex Def = LR.getValNumInfo(i)->def;
// Print message so mismatches with eraseInstrs() can be diagnosed.
DEBUG(dbgs() << "\t\tExpecting instruction removal at " << Def << '\n');
for (LiveInterval::SubRange &S : LI.subranges()) {
LiveQueryResult Q = S.Query(Def);

31
test/CodeGen/AMDGPU/regcoalesce-prune.mir Normal file
View File

@ -0,0 +1,31 @@
# RUN: llc -o - %s -mtriple=amdgcn-amd-amdhsa-opencl -run-pass=simple-register-coalescing | FileCheck %s
---
# Checks for a bug where subregister liveranges were not properly pruned for
# an IMPLCITI_DEF that gets removed completely.
#
# CHECK-LABEL: name: func
# IMPLICIT_DEF should be gone without llc hitting assertion failures.
# CHECK-NOT: IMPLCITI_DEF
name: func
tracksRegLiveness: true
body: |
bb.0:
undef %5.sub1 = V_MOV_B32_e32 0, implicit %exec
%6 = COPY %5
S_CBRANCH_VCCZ %bb.2, implicit undef %vcc
bb.1:
%1 : sreg_32_xm0 = S_MOV_B32 0
undef %0.sub0 : sreg_64 = COPY %1
%0.sub1 = COPY %1
%4 : vreg_64 = COPY killed %0
%5 : vreg_64 = IMPLICIT_DEF
%6 : vreg_64 = COPY killed %4
bb.2:
%2 : vgpr_32 = V_CVT_F32_I32_e32 killed %5.sub1, implicit %exec
bb.3:
%3 : vgpr_32 = V_CVT_F32_I32_e32 killed %6.sub1, implicit %exec
S_ENDPGM
...