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factor code better in X86MCInstLower::Lower, teach it to
lower the SETB* instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95431 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -302,6 +302,17 @@ static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) {
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}
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}
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/// LowerMOVxX32 - Things like MOVZX16rr8 -> MOVZX32rr8.
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static void LowerMOVxX32(MCInst &OutMI, unsigned NewOpc) {
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OutMI.setOpcode(NewOpc);
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lower_subreg32(&OutMI, 0);
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}
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/// LowerSETB - R = setb -> R = sbb R, R
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static void LowerSETB(MCInst &OutMI, unsigned NewOpc) {
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OutMI.setOpcode(NewOpc);
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OutMI.addOperand(OutMI.getOperand(0));
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OutMI.addOperand(OutMI.getOperand(0));
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}
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void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
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@ -352,50 +363,17 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
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case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand.
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lower_lea64_32mem(&OutMI, 1);
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break;
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case X86::MOVZX16rr8:
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OutMI.setOpcode(X86::MOVZX32rr8);
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lower_subreg32(&OutMI, 0);
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break;
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case X86::MOVZX16rm8:
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OutMI.setOpcode(X86::MOVZX32rm8);
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lower_subreg32(&OutMI, 0);
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break;
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case X86::MOVSX16rr8:
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OutMI.setOpcode(X86::MOVSX32rr8);
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lower_subreg32(&OutMI, 0);
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break;
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case X86::MOVSX16rm8:
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OutMI.setOpcode(X86::MOVSX32rm8);
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lower_subreg32(&OutMI, 0);
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break;
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case X86::MOVZX64rr32:
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OutMI.setOpcode(X86::MOV32rr);
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lower_subreg32(&OutMI, 0);
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break;
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case X86::MOVZX64rm32:
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OutMI.setOpcode(X86::MOV32rm);
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lower_subreg32(&OutMI, 0);
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break;
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case X86::MOV64ri64i32:
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OutMI.setOpcode(X86::MOV32ri);
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lower_subreg32(&OutMI, 0);
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break;
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case X86::MOVZX64rr8:
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OutMI.setOpcode(X86::MOVZX32rr8);
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lower_subreg32(&OutMI, 0);
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break;
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case X86::MOVZX64rm8:
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OutMI.setOpcode(X86::MOVZX32rm8);
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lower_subreg32(&OutMI, 0);
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break;
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case X86::MOVZX64rr16:
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OutMI.setOpcode(X86::MOVZX32rr16);
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lower_subreg32(&OutMI, 0);
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break;
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case X86::MOVZX64rm16:
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OutMI.setOpcode(X86::MOVZX32rm16);
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lower_subreg32(&OutMI, 0);
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break;
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case X86::MOVZX16rr8: LowerMOVxX32(OutMI, X86::MOVZX32rr8); break;
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case X86::MOVZX16rm8: LowerMOVxX32(OutMI, X86::MOVZX32rm8); break;
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case X86::MOVSX16rr8: LowerMOVxX32(OutMI, X86::MOVSX32rr8); break;
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case X86::MOVSX16rm8: LowerMOVxX32(OutMI, X86::MOVSX32rm8); break;
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case X86::MOVZX64rr32: LowerMOVxX32(OutMI, X86::MOV32rr); break;
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case X86::MOVZX64rm32: LowerMOVxX32(OutMI, X86::MOV32rm); break;
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case X86::MOV64ri64i32: LowerMOVxX32(OutMI, X86::MOV32ri); break;
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case X86::MOVZX64rr8: LowerMOVxX32(OutMI, X86::MOVZX32rr8); break;
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case X86::MOVZX64rm8: LowerMOVxX32(OutMI, X86::MOVZX32rm8); break;
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case X86::MOVZX64rr16: LowerMOVxX32(OutMI, X86::MOVZX32rr16); break;
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case X86::MOVZX64rm16: LowerMOVxX32(OutMI, X86::MOVZX32rm16); break;
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case X86::MOV16r0:
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OutMI.setOpcode(X86::MOV32r0);
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lower_subreg32(&OutMI, 0);
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@ -404,6 +382,10 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
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OutMI.setOpcode(X86::MOV32r0);
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lower_subreg32(&OutMI, 0);
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break;
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case X86::SETB_C8r: LowerSETB(OutMI, X86::SBB8rr); break;
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case X86::SETB_C16r: LowerSETB(OutMI, X86::SBB16rr); break;
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case X86::SETB_C32r: LowerSETB(OutMI, X86::SBB32rr); break;
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case X86::SETB_C64r: LowerSETB(OutMI, X86::SBB64rr); break;
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}
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}
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@ -1466,9 +1466,13 @@ def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
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} // isTwoAddress
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// Use sbb to materialize carry flag into a GPR.
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// FIXME: This are pseudo ops that should be replaced with Pat<> patterns.
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// However, Pat<> can't replicate the destination reg into the inputs of the
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// result.
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// FIXME: Change this to have encoding Pseudo when X86MCCodeEmitter replaces
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// X86CodeEmitter.
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let Defs = [EFLAGS], Uses = [EFLAGS], isCodeGenOnly = 1 in
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def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins),
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"sbb{q}\t$dst, $dst",
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def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
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[(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
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def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
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@ -3256,17 +3256,18 @@ def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
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let Uses = [EFLAGS] in {
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// Use sbb to materialize carry bit.
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let Defs = [EFLAGS], isCodeGenOnly = 1 in {
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def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins),
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"sbb{b}\t$dst, $dst",
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// FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
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// However, Pat<> can't replicate the destination reg into the inputs of the
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// result.
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// FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
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// X86CodeEmitter.
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def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
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[(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
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def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins),
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"sbb{w}\t$dst, $dst",
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def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
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[(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
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OpSize;
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def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins),
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"sbb{l}\t$dst, $dst",
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def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
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[(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
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} // isCodeGenOnly
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