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factor code better in X86MCInstLower::Lower, teach it to

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lower the SETB* instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95431 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-02-05 21:13:48 +00:00
parent 74529826a7
commit c74e333ecc
3 changed files with 40 additions and 53 deletions
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70
lib/Target/X86/AsmPrinter/X86MCInstLower.cpp
View File

@ -302,6 +302,17 @@ static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) {
}
}
/// LowerMOVxX32 - Things like MOVZX16rr8 -> MOVZX32rr8.
static void LowerMOVxX32(MCInst &OutMI, unsigned NewOpc) {
OutMI.setOpcode(NewOpc);
lower_subreg32(&OutMI, 0);
}
/// LowerSETB - R = setb -> R = sbb R, R
static void LowerSETB(MCInst &OutMI, unsigned NewOpc) {
OutMI.setOpcode(NewOpc);
OutMI.addOperand(OutMI.getOperand(0));
OutMI.addOperand(OutMI.getOperand(0));
}
void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
@ -352,50 +363,17 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand.
lower_lea64_32mem(&OutMI, 1);
break;
case X86::MOVZX16rr8:
OutMI.setOpcode(X86::MOVZX32rr8);
lower_subreg32(&OutMI, 0);
break;
case X86::MOVZX16rm8:
OutMI.setOpcode(X86::MOVZX32rm8);
lower_subreg32(&OutMI, 0);
break;
case X86::MOVSX16rr8:
OutMI.setOpcode(X86::MOVSX32rr8);
lower_subreg32(&OutMI, 0);
break;
case X86::MOVSX16rm8:
OutMI.setOpcode(X86::MOVSX32rm8);
lower_subreg32(&OutMI, 0);
break;
case X86::MOVZX64rr32:
OutMI.setOpcode(X86::MOV32rr);
lower_subreg32(&OutMI, 0);
break;
case X86::MOVZX64rm32:
OutMI.setOpcode(X86::MOV32rm);
lower_subreg32(&OutMI, 0);
break;
case X86::MOV64ri64i32:
OutMI.setOpcode(X86::MOV32ri);
lower_subreg32(&OutMI, 0);
break;
case X86::MOVZX64rr8:
OutMI.setOpcode(X86::MOVZX32rr8);
lower_subreg32(&OutMI, 0);
break;
case X86::MOVZX64rm8:
OutMI.setOpcode(X86::MOVZX32rm8);
lower_subreg32(&OutMI, 0);
break;
case X86::MOVZX64rr16:
OutMI.setOpcode(X86::MOVZX32rr16);
lower_subreg32(&OutMI, 0);
break;
case X86::MOVZX64rm16:
OutMI.setOpcode(X86::MOVZX32rm16);
lower_subreg32(&OutMI, 0);
break;
case X86::MOVZX16rr8: LowerMOVxX32(OutMI, X86::MOVZX32rr8); break;
case X86::MOVZX16rm8: LowerMOVxX32(OutMI, X86::MOVZX32rm8); break;
case X86::MOVSX16rr8: LowerMOVxX32(OutMI, X86::MOVSX32rr8); break;
case X86::MOVSX16rm8: LowerMOVxX32(OutMI, X86::MOVSX32rm8); break;
case X86::MOVZX64rr32: LowerMOVxX32(OutMI, X86::MOV32rr); break;
case X86::MOVZX64rm32: LowerMOVxX32(OutMI, X86::MOV32rm); break;
case X86::MOV64ri64i32: LowerMOVxX32(OutMI, X86::MOV32ri); break;
case X86::MOVZX64rr8: LowerMOVxX32(OutMI, X86::MOVZX32rr8); break;
case X86::MOVZX64rm8: LowerMOVxX32(OutMI, X86::MOVZX32rm8); break;
case X86::MOVZX64rr16: LowerMOVxX32(OutMI, X86::MOVZX32rr16); break;
case X86::MOVZX64rm16: LowerMOVxX32(OutMI, X86::MOVZX32rm16); break;
case X86::MOV16r0:
OutMI.setOpcode(X86::MOV32r0);
lower_subreg32(&OutMI, 0);
@ -404,6 +382,10 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
OutMI.setOpcode(X86::MOV32r0);
lower_subreg32(&OutMI, 0);
break;
case X86::SETB_C8r: LowerSETB(OutMI, X86::SBB8rr); break;
case X86::SETB_C16r: LowerSETB(OutMI, X86::SBB16rr); break;
case X86::SETB_C32r: LowerSETB(OutMI, X86::SBB32rr); break;
case X86::SETB_C64r: LowerSETB(OutMI, X86::SBB64rr); break;
}
}

8
lib/Target/X86/X86Instr64bit.td
View File

@ -1466,9 +1466,13 @@ def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
} // isTwoAddress
// Use sbb to materialize carry flag into a GPR.
// FIXME: This are pseudo ops that should be replaced with Pat<> patterns.
// However, Pat<> can't replicate the destination reg into the inputs of the
// result.
// FIXME: Change this to have encoding Pseudo when X86MCCodeEmitter replaces
// X86CodeEmitter.
let Defs = [EFLAGS], Uses = [EFLAGS], isCodeGenOnly = 1 in
def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins),
"sbb{q}\t$dst, $dst",
def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
[(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),

15
lib/Target/X86/X86InstrInfo.td
View File

@ -3256,17 +3256,18 @@ def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
let Uses = [EFLAGS] in {
// Use sbb to materialize carry bit.
let Defs = [EFLAGS], isCodeGenOnly = 1 in {
def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins),
"sbb{b}\t$dst, $dst",
// FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
// However, Pat<> can't replicate the destination reg into the inputs of the
// result.
// FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
// X86CodeEmitter.
def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
[(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins),
"sbb{w}\t$dst, $dst",
def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
[(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
OpSize;
def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins),
"sbb{l}\t$dst, $dst",
def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
[(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
} // isCodeGenOnly