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Add instruction encodings / disassembly support for l3r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne
parent
a68c64fbb2
commit
c78ec6b6bc
@ -147,6 +147,16 @@ static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeL3RInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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#include "XCoreGenDisassemblerTables.inc"
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static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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@ -353,16 +363,73 @@ DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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return S;
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}
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static DecodeStatus
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DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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// Try and decode as a L3R instruction.
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unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
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fieldFromInstruction(Insn, 27, 5) << 4;
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switch (Opcode) {
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case 0x0c:
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Inst.setOpcode(XCore::STW_3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x1c:
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Inst.setOpcode(XCore::XOR_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x2c:
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Inst.setOpcode(XCore::ASHR_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x3c:
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Inst.setOpcode(XCore::LDAWF_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x4c:
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Inst.setOpcode(XCore::LDAWB_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x5c:
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Inst.setOpcode(XCore::LDA16F_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x6c:
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Inst.setOpcode(XCore::LDA16B_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x7c:
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Inst.setOpcode(XCore::MUL_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x8c:
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Inst.setOpcode(XCore::DIVS_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x9c:
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Inst.setOpcode(XCore::DIVU_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x10c:
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Inst.setOpcode(XCore::ST16_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x11c:
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Inst.setOpcode(XCore::ST8_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x15c:
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Inst.setOpcode(XCore::CRC_l3r);
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return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
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case 0x18c:
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Inst.setOpcode(XCore::REMS_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x19c:
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Inst.setOpcode(XCore::REMU_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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}
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return MCDisassembler::Fail;
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}
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static DecodeStatus
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DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
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Op1, Op2);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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}
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if (S != MCDisassembler::Success)
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return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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return S;
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}
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@ -372,10 +439,11 @@ DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
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Op1, Op2);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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}
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if (S != MCDisassembler::Success)
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return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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return S;
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}
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@ -418,6 +486,35 @@ Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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return S;
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}
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static DecodeStatus
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DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2, Op3;
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DecodeStatus S =
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Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
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}
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return S;
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}
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static DecodeStatus
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DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2, Op3;
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DecodeStatus S =
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Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
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}
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return S;
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}
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MCDisassembler::DecodeStatus
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XCoreDisassembler::getInstruction(MCInst &instr,
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uint64_t &Size,
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@ -39,8 +39,20 @@ class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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let DecoderMethod = "Decode3RInstruction";
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}
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class _FL3R<dag outs, dag ins, string asmstr, list<dag> pattern>
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class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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let Inst{31-27} = opc{8-4};
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let Inst{26-20} = 0b1111110;
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let Inst{19-16} = opc{3-0};
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let Inst{15-11} = 0b11111;
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let DecoderMethod = "DecodeL3RInstruction";
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}
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// L3R with first operand as both a source and a destination.
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class _FL3RSrcDst<bits<9> opc, dag outs, dag ins, string asmstr,
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list<dag> pattern> : _FL3R<opc, outs, ins, asmstr, pattern> {
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let DecoderMethod = "DecodeL3RSrcDstInstruction";
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}
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class _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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@ -237,11 +237,10 @@ class F3R_np<bits<5> opc, string OpcStr> :
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// Three operand long
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/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
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multiclass FL3R_L2RUS<string OpcStr, SDNode OpNode> {
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def _l3r: _FL3R<
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(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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multiclass FL3R_L2RUS<bits<9> opc, string OpcStr, SDNode OpNode> {
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def _l3r: _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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def _l2rus : _FL2RUS<
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(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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@ -249,21 +248,20 @@ multiclass FL3R_L2RUS<string OpcStr, SDNode OpNode> {
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}
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/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
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multiclass FL3R_L2RBITP<string OpcStr, SDNode OpNode> {
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def _l3r: _FL3R<
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(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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multiclass FL3R_L2RBITP<bits<9> opc, string OpcStr, SDNode OpNode> {
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def _l3r: _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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def _l2rus : _FL2RUS<
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(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
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}
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class FL3R<string OpcStr, SDNode OpNode> : _FL3R<
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(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> :
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_FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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// Register - U6
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// Operand register - U6
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@ -411,8 +409,9 @@ def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst),
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}
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let mayStore=1 in {
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def STW_3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
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"stw $val, $addr[$offset]", []>;
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def STW_3r : _FL3R<0b000001100, (outs),
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(ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
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"stw $val, $addr[$offset]", []>;
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def STW_2rus : _F2RUS<0b0000, (outs),
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(ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
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@ -424,9 +423,11 @@ defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>;
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// TODO tsetr
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// Three operand long
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def LDAWF_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
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"ldaw $dst, $addr[$offset]",
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[(set GRRegs:$dst, (ldawf GRRegs:$addr, GRRegs:$offset))]>;
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def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst),
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(ins GRRegs:$addr, GRRegs:$offset),
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"ldaw $dst, $addr[$offset]",
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[(set GRRegs:$dst,
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(ldawf GRRegs:$addr, GRRegs:$offset))]>;
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let neverHasSideEffects = 1 in
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def LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst),
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@ -434,9 +435,11 @@ def LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst),
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"ldaw $dst, $addr[$offset]",
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[]>;
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def LDAWB_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
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"ldaw $dst, $addr[-$offset]",
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[(set GRRegs:$dst, (ldawb GRRegs:$addr, GRRegs:$offset))]>;
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def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst),
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(ins GRRegs:$addr, GRRegs:$offset),
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"ldaw $dst, $addr[-$offset]",
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[(set GRRegs:$dst,
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(ldawb GRRegs:$addr, GRRegs:$offset))]>;
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let neverHasSideEffects = 1 in
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def LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst),
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@ -444,42 +447,46 @@ def LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst),
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"ldaw $dst, $addr[-$offset]",
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[]>;
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def LDA16F_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
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"lda16 $dst, $addr[$offset]",
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[(set GRRegs:$dst, (lda16f GRRegs:$addr, GRRegs:$offset))]>;
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def LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst),
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(ins GRRegs:$addr, GRRegs:$offset),
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"lda16 $dst, $addr[$offset]",
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[(set GRRegs:$dst,
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(lda16f GRRegs:$addr, GRRegs:$offset))]>;
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def LDA16B_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
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"lda16 $dst, $addr[-$offset]",
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[(set GRRegs:$dst, (lda16b GRRegs:$addr, GRRegs:$offset))]>;
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def LDA16B_l3r : _FL3R<0b001101100, (outs GRRegs:$dst),
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(ins GRRegs:$addr, GRRegs:$offset),
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"lda16 $dst, $addr[-$offset]",
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[(set GRRegs:$dst,
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(lda16b GRRegs:$addr, GRRegs:$offset))]>;
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def MUL_l3r : FL3R<"mul", mul>;
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def MUL_l3r : FL3R<0b001111100, "mul", mul>;
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// Instructions which may trap are marked as side effecting.
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let hasSideEffects = 1 in {
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def DIVS_l3r : FL3R<"divs", sdiv>;
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def DIVU_l3r : FL3R<"divu", udiv>;
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def REMS_l3r : FL3R<"rems", srem>;
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def REMU_l3r : FL3R<"remu", urem>;
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def DIVS_l3r : FL3R<0b010001100, "divs", sdiv>;
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def DIVU_l3r : FL3R<0b010011100, "divu", udiv>;
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def REMS_l3r : FL3R<0b110001100, "rems", srem>;
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def REMU_l3r : FL3R<0b110011100, "remu", urem>;
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}
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def XOR_l3r : FL3R<"xor", xor>;
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defm ASHR : FL3R_L2RBITP<"ashr", sra>;
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def XOR_l3r : FL3R<0b000011100, "xor", xor>;
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defm ASHR : FL3R_L2RBITP<0b000101100, "ashr", sra>;
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let Constraints = "$src1 = $dst" in
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def CRC_l3r : _FL3R<(outs GRRegs:$dst),
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(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
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"crc32 $dst, $src2, $src3",
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[(set GRRegs:$dst,
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(int_xcore_crc32 GRRegs:$src1, GRRegs:$src2,
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GRRegs:$src3))]>;
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def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst),
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(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
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"crc32 $dst, $src2, $src3",
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[(set GRRegs:$dst,
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(int_xcore_crc32 GRRegs:$src1, GRRegs:$src2,
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GRRegs:$src3))]>;
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// TODO inpw, outpw
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let mayStore=1 in {
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def ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
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"st16 $val, $addr[$offset]",
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[]>;
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def ST16_l3r : _FL3R<0b100001100, (outs),
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(ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
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"st16 $val, $addr[$offset]", []>;
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def ST8_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
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"st8 $val, $addr[$offset]",
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[]>;
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def ST8_l3r : _FL3R<0b100011100, (outs),
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(ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
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"st8 $val, $addr[$offset]", []>;
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}
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// Four operand long
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@ -257,3 +257,47 @@
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# CHECK: sub r2, r4, 11
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0x63 0x9d
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# l3r instructions
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# CHECK: ashr r5, r1, r11
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0xd7 0xfc 0xec 0x17
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# CHECK: crc32 r5, r6, r1
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0x19 0xf9 0xec 0xaf
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# CHECK: divu r9, r1, r3
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0x97 0xf8 0xec 0x4f
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# CHECK: divs r6, r7, r2
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0x2e 0xf9 0xec 0x47
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# CHECK: lda16 r11, r2[r1]
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0xb9 0xf8 0xec 0x2f
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# CHECK: lda16 r9, r3[-r11]
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0x1f 0xfd 0xec 0x37
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# CHECK: ldaw r9, r1[r2]
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0x96 0xf8 0xec 0x1f
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# CHECK: ldaw r8, r7[r11]
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0xcf 0xfd 0xec 0x1f
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# CHECK: mul r0, r4, r2
|
||||
0xc2 0xf8 0xec 0x3f
|
||||
|
||||
# CHECK: remu r1, r2, r3
|
||||
0x1b 0xf8 0xec 0xcf
|
||||
|
||||
# CHECK: rems r11, r10, r9
|
||||
0xb9 0xfe 0xec 0xc7
|
||||
|
||||
# CHECK: st16 r5, r3[r8]
|
||||
0xdc 0xfc 0xec 0x87
|
||||
|
||||
# CHECK: stw r7, r10[r1]
|
||||
0xf9 0xf9 0xec 0x07
|
||||
|
||||
# CHECK: xor r4, r3, r9
|
||||
0xcd 0xfc 0xec 0x0f
|
||||
|
||||
Loading…
Reference in New Issue
Block a user