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Add instruction encodings / disassembly support for l3r instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2013-01-20 18:37:49 +00:00
parent a68c64fbb2
commit c78ec6b6bc
4 changed files with 216 additions and 56 deletions
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113
lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
View File

@ -147,6 +147,16 @@ static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeL3RInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
#include "XCoreGenDisassemblerTables.inc" #include "XCoreGenDisassemblerTables.inc"
static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
@ -353,16 +363,73 @@ DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
return S; return S;
} }
static DecodeStatus
DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
// Try and decode as a L3R instruction.
unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
fieldFromInstruction(Insn, 27, 5) << 4;
switch (Opcode) {
case 0x0c:
Inst.setOpcode(XCore::STW_3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x1c:
Inst.setOpcode(XCore::XOR_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x2c:
Inst.setOpcode(XCore::ASHR_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x3c:
Inst.setOpcode(XCore::LDAWF_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x4c:
Inst.setOpcode(XCore::LDAWB_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x5c:
Inst.setOpcode(XCore::LDA16F_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x6c:
Inst.setOpcode(XCore::LDA16B_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x7c:
Inst.setOpcode(XCore::MUL_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x8c:
Inst.setOpcode(XCore::DIVS_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x9c:
Inst.setOpcode(XCore::DIVU_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x10c:
Inst.setOpcode(XCore::ST16_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x11c:
Inst.setOpcode(XCore::ST8_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x15c:
Inst.setOpcode(XCore::CRC_l3r);
return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
case 0x18c:
Inst.setOpcode(XCore::REMS_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x19c:
Inst.setOpcode(XCore::REMU_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
}
return MCDisassembler::Fail;
}
static DecodeStatus static DecodeStatus
DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2; unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16), DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
Op1, Op2); Op1, Op2);
if (S == MCDisassembler::Success) { if (S != MCDisassembler::Success)
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
} DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
return S; return S;
} }
@ -372,10 +439,11 @@ DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
unsigned Op1, Op2; unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16), DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
Op1, Op2); Op1, Op2);
if (S == MCDisassembler::Success) { if (S != MCDisassembler::Success)
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
} DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
return S; return S;
} }
@ -418,6 +486,35 @@ Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
return S; return S;
} }
static DecodeStatus
DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3;
DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
}
return S;
}
static DecodeStatus
DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3;
DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
}
return S;
}
MCDisassembler::DecodeStatus MCDisassembler::DecodeStatus
XCoreDisassembler::getInstruction(MCInst &instr, XCoreDisassembler::getInstruction(MCInst &instr,
uint64_t &Size, uint64_t &Size,

14
lib/Target/XCore/XCoreInstrFormats.td
View File

@ -39,8 +39,20 @@ class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
let DecoderMethod = "Decode3RInstruction"; let DecoderMethod = "Decode3RInstruction";
} }
class _FL3R<dag outs, dag ins, string asmstr, list<dag> pattern> class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> { : InstXCore<4, outs, ins, asmstr, pattern> {
let Inst{31-27} = opc{8-4};
let Inst{26-20} = 0b1111110;
let Inst{19-16} = opc{3-0};
let Inst{15-11} = 0b11111;
let DecoderMethod = "DecodeL3RInstruction";
}
// L3R with first operand as both a source and a destination.
class _FL3RSrcDst<bits<9> opc, dag outs, dag ins, string asmstr,
list<dag> pattern> : _FL3R<opc, outs, ins, asmstr, pattern> {
let DecoderMethod = "DecodeL3RSrcDstInstruction";
} }
class _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern> class _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>

101
lib/Target/XCore/XCoreInstrInfo.td
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@ -237,11 +237,10 @@ class F3R_np<bits<5> opc, string OpcStr> :
// Three operand long // Three operand long
/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
multiclass FL3R_L2RUS<string OpcStr, SDNode OpNode> { multiclass FL3R_L2RUS<bits<9> opc, string OpcStr, SDNode OpNode> {
def _l3r: _FL3R< def _l3r: _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), !strconcat(OpcStr, " $dst, $b, $c"),
!strconcat(OpcStr, " $dst, $b, $c"), [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
def _l2rus : _FL2RUS< def _l2rus : _FL2RUS<
(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
!strconcat(OpcStr, " $dst, $b, $c"), !strconcat(OpcStr, " $dst, $b, $c"),
@ -249,21 +248,20 @@ multiclass FL3R_L2RUS<string OpcStr, SDNode OpNode> {
} }
/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
multiclass FL3R_L2RBITP<string OpcStr, SDNode OpNode> { multiclass FL3R_L2RBITP<bits<9> opc, string OpcStr, SDNode OpNode> {
def _l3r: _FL3R< def _l3r: _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), !strconcat(OpcStr, " $dst, $b, $c"),
!strconcat(OpcStr, " $dst, $b, $c"), [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
def _l2rus : _FL2RUS< def _l2rus : _FL2RUS<
(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
!strconcat(OpcStr, " $dst, $b, $c"), !strconcat(OpcStr, " $dst, $b, $c"),
[(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
} }
class FL3R<string OpcStr, SDNode OpNode> : _FL3R< class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> :
(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
!strconcat(OpcStr, " $dst, $b, $c"), !strconcat(OpcStr, " $dst, $b, $c"),
[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
// Register - U6 // Register - U6
// Operand register - U6 // Operand register - U6
@ -411,8 +409,9 @@ def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst),
} }
let mayStore=1 in { let mayStore=1 in {
def STW_3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), def STW_3r : _FL3R<0b000001100, (outs),
"stw $val, $addr[$offset]", []>; (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
"stw $val, $addr[$offset]", []>;
def STW_2rus : _F2RUS<0b0000, (outs), def STW_2rus : _F2RUS<0b0000, (outs),
(ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
@ -424,9 +423,11 @@ defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>;
// TODO tsetr // TODO tsetr
// Three operand long // Three operand long
def LDAWF_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst),
"ldaw $dst, $addr[$offset]", (ins GRRegs:$addr, GRRegs:$offset),
[(set GRRegs:$dst, (ldawf GRRegs:$addr, GRRegs:$offset))]>; "ldaw $dst, $addr[$offset]",
[(set GRRegs:$dst,
(ldawf GRRegs:$addr, GRRegs:$offset))]>;
let neverHasSideEffects = 1 in let neverHasSideEffects = 1 in
def LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst), def LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst),
@ -434,9 +435,11 @@ def LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst),
"ldaw $dst, $addr[$offset]", "ldaw $dst, $addr[$offset]",
[]>; []>;
def LDAWB_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst),
"ldaw $dst, $addr[-$offset]", (ins GRRegs:$addr, GRRegs:$offset),
[(set GRRegs:$dst, (ldawb GRRegs:$addr, GRRegs:$offset))]>; "ldaw $dst, $addr[-$offset]",
[(set GRRegs:$dst,
(ldawb GRRegs:$addr, GRRegs:$offset))]>;
let neverHasSideEffects = 1 in let neverHasSideEffects = 1 in
def LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst), def LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst),
@ -444,42 +447,46 @@ def LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst),
"ldaw $dst, $addr[-$offset]", "ldaw $dst, $addr[-$offset]",
[]>; []>;
def LDA16F_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), def LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst),
"lda16 $dst, $addr[$offset]", (ins GRRegs:$addr, GRRegs:$offset),
[(set GRRegs:$dst, (lda16f GRRegs:$addr, GRRegs:$offset))]>; "lda16 $dst, $addr[$offset]",
[(set GRRegs:$dst,
(lda16f GRRegs:$addr, GRRegs:$offset))]>;
def LDA16B_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), def LDA16B_l3r : _FL3R<0b001101100, (outs GRRegs:$dst),
"lda16 $dst, $addr[-$offset]", (ins GRRegs:$addr, GRRegs:$offset),
[(set GRRegs:$dst, (lda16b GRRegs:$addr, GRRegs:$offset))]>; "lda16 $dst, $addr[-$offset]",
[(set GRRegs:$dst,
(lda16b GRRegs:$addr, GRRegs:$offset))]>;
def MUL_l3r : FL3R<"mul", mul>; def MUL_l3r : FL3R<0b001111100, "mul", mul>;
// Instructions which may trap are marked as side effecting. // Instructions which may trap are marked as side effecting.
let hasSideEffects = 1 in { let hasSideEffects = 1 in {
def DIVS_l3r : FL3R<"divs", sdiv>; def DIVS_l3r : FL3R<0b010001100, "divs", sdiv>;
def DIVU_l3r : FL3R<"divu", udiv>; def DIVU_l3r : FL3R<0b010011100, "divu", udiv>;
def REMS_l3r : FL3R<"rems", srem>; def REMS_l3r : FL3R<0b110001100, "rems", srem>;
def REMU_l3r : FL3R<"remu", urem>; def REMU_l3r : FL3R<0b110011100, "remu", urem>;
} }
def XOR_l3r : FL3R<"xor", xor>; def XOR_l3r : FL3R<0b000011100, "xor", xor>;
defm ASHR : FL3R_L2RBITP<"ashr", sra>; defm ASHR : FL3R_L2RBITP<0b000101100, "ashr", sra>;
let Constraints = "$src1 = $dst" in let Constraints = "$src1 = $dst" in
def CRC_l3r : _FL3R<(outs GRRegs:$dst), def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst),
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
"crc32 $dst, $src2, $src3", "crc32 $dst, $src2, $src3",
[(set GRRegs:$dst, [(set GRRegs:$dst,
(int_xcore_crc32 GRRegs:$src1, GRRegs:$src2, (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2,
GRRegs:$src3))]>; GRRegs:$src3))]>;
// TODO inpw, outpw // TODO inpw, outpw
let mayStore=1 in { let mayStore=1 in {
def ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), def ST16_l3r : _FL3R<0b100001100, (outs),
"st16 $val, $addr[$offset]", (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
[]>; "st16 $val, $addr[$offset]", []>;
def ST8_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), def ST8_l3r : _FL3R<0b100011100, (outs),
"st8 $val, $addr[$offset]", (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
[]>; "st8 $val, $addr[$offset]", []>;
} }
// Four operand long // Four operand long

44
test/MC/Disassembler/XCore/xcore.txt
View File

@ -257,3 +257,47 @@
# CHECK: sub r2, r4, 11 # CHECK: sub r2, r4, 11
0x63 0x9d 0x63 0x9d
# l3r instructions
# CHECK: ashr r5, r1, r11
0xd7 0xfc 0xec 0x17
# CHECK: crc32 r5, r6, r1
0x19 0xf9 0xec 0xaf
# CHECK: divu r9, r1, r3
0x97 0xf8 0xec 0x4f
# CHECK: divs r6, r7, r2
0x2e 0xf9 0xec 0x47
# CHECK: lda16 r11, r2[r1]
0xb9 0xf8 0xec 0x2f
# CHECK: lda16 r9, r3[-r11]
0x1f 0xfd 0xec 0x37
# CHECK: ldaw r9, r1[r2]
0x96 0xf8 0xec 0x1f
# CHECK: ldaw r8, r7[r11]
0xcf 0xfd 0xec 0x1f
# CHECK: mul r0, r4, r2
0xc2 0xf8 0xec 0x3f
# CHECK: remu r1, r2, r3
0x1b 0xf8 0xec 0xcf
# CHECK: rems r11, r10, r9
0xb9 0xfe 0xec 0xc7
# CHECK: st16 r5, r3[r8]
0xdc 0xfc 0xec 0x87
# CHECK: stw r7, r10[r1]
0xf9 0xf9 0xec 0x07
# CHECK: xor r4, r3, r9
0xcd 0xfc 0xec 0x0f