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Add definitions of Mips64 rotate instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140870 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-09-30 18:51:46 +00:00
parent cbf676b3ba
commit c7bafe9241
3 changed files with 64 additions and 2 deletions
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20
lib/Target/Mips/Mips64InstrInfo.td
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@ -116,4 +116,22 @@ def DSRL32 : LogicR_shift_rotate_imm64<0x3e, 0x00, "dsrl32", srl, imm32_63>;
def DSRA32 : LogicR_shift_rotate_imm64<0x3f, 0x00, "dsra32", sra, imm32_63>;
def DSLLV : LogicR_shift_rotate_reg64<0x24, 0x00, "dsllv", shl>;
def DSRLV : LogicR_shift_rotate_reg64<0x26, 0x00, "dsrlv", srl>;
def DSRAV : LogicR_shift_rotate_reg64<0x27, 0x00, "dsrav", sra>;
def DSRAV : LogicR_shift_rotate_reg64<0x27, 0x00, "dsrav", sra>;
// Rotate Instructions
let Predicates = [HasMips64r2] in {
def DROTR : LogicR_shift_rotate_imm64<0x3a, 0x01, "drotr", rotr, immZExt5>;
def DROTR32 : LogicR_shift_rotate_imm64<0x3e, 0x01, "drotr32", rotr,
imm32_63>;
def DROTRV : LogicR_shift_rotate_reg64<0x16, 0x01, "drotrv", rotr>;
}
//===----------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===//
// Small immediates
def : Pat<(i64 immSExt16:$in),
(DADDiu ZERO_64, imm:$in)>;
def : Pat<(i64 immZExt16:$in),
(DORi ZERO_64, imm:$in)>;

4
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -149,10 +149,14 @@ MipsTargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::CTPOP, MVT::i32, Expand);
setOperationAction(ISD::CTTZ, MVT::i32, Expand);
setOperationAction(ISD::ROTL, MVT::i32, Expand);
setOperationAction(ISD::ROTL, MVT::i64, Expand);
if (!Subtarget->hasMips32r2())
setOperationAction(ISD::ROTR, MVT::i32, Expand);
if (!Subtarget->hasMips64r2())
setOperationAction(ISD::ROTR, MVT::i64, Expand);
setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);

42
test/CodeGen/Mips/mips64shift.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=mips64el -mcpu=mips64r1 < %s | FileCheck %s
; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s
define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
entry:
@ -62,3 +62,43 @@ entry:
%shr = lshr i64 %a0, 40
ret i64 %shr
}
define i64 @f9(i64 %a0, i64 %a1) nounwind readnone {
entry:
; CHECK: drotrv
%shr = lshr i64 %a0, %a1
%sub = sub i64 64, %a1
%shl = shl i64 %a0, %sub
%or = or i64 %shl, %shr
ret i64 %or
}
define i64 @f10(i64 %a0, i64 %a1) nounwind readnone {
entry:
; CHECK: drotrv
%shl = shl i64 %a0, %a1
%sub = sub i64 64, %a1
%shr = lshr i64 %a0, %sub
%or = or i64 %shr, %shl
ret i64 %or
}
define i64 @f11(i64 %a0) nounwind readnone {
entry:
; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10
%shr = lshr i64 %a0, 10
%shl = shl i64 %a0, 54
%or = or i64 %shr, %shl
ret i64 %or
}
define i64 @f12(i64 %a0) nounwind readnone {
entry:
; CHECK: drotr32 ${{[0-9]+}}, ${{[0-9]+}}, 22
%shl = shl i64 %a0, 10
%shr = lshr i64 %a0, 54
%or = or i64 %shl, %shr
ret i64 %or
}