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Add optimization bisect opt-in calls for AMDGPU passes

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Differential Revision: http://reviews.llvm.org/D19450



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267485 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Kaylor 2016-04-25 22:23:44 +00:00
parent 3c50cf9777
commit c7ca1302cf
7 changed files with 19 additions and 1 deletions
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3
lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
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@ -88,6 +88,9 @@ bool AMDGPUAnnotateUniformValues::doInitialization(Module &M) {
}
bool AMDGPUAnnotateUniformValues::runOnFunction(Function &F) {
if (skipFunction(F))
return false;
DA = &getAnalysis<DivergenceAnalysis>();
visit(F);

2
lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
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@ -97,7 +97,7 @@ bool AMDGPUPromoteAlloca::doInitialization(Module &M) {
}
bool AMDGPUPromoteAlloca::runOnFunction(Function &F) {
if (!TM || F.hasFnAttribute(Attribute::OptimizeNone))
if (!TM || skipFunction(F))
return false;
FunctionType *FTy = F.getFunctionType();

3
lib/Target/AMDGPU/R600ClauseMergePass.cpp
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@ -168,6 +168,9 @@ bool R600ClauseMergePass::mergeIfPossible(MachineInstr *RootCFAlu,
}
bool R600ClauseMergePass::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
return false;
TII = static_cast<const R600InstrInfo *>(MF.getSubtarget().getInstrInfo());
for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
BB != BB_E; ++BB) {

3
lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
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@ -314,6 +314,9 @@ void R600VectorRegMerger::trackRSI(const RegSeqInfo &RSI) {
}
bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) {
if (skipFunction(*Fn.getFunction()))
return false;
TII = static_cast<const R600InstrInfo *>(Fn.getSubtarget().getInstrInfo());
MRI = &(Fn.getRegInfo());
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();

3
lib/Target/AMDGPU/SIFoldOperands.cpp
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@ -295,6 +295,9 @@ static void foldOperand(MachineOperand &OpToFold, MachineInstr *UseMI,
}
bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
return false;
MachineRegisterInfo &MRI = MF.getRegInfo();
const SIInstrInfo *TII =
static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());

3
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
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@ -423,6 +423,9 @@ bool SILoadStoreOptimizer::optimizeBlock(MachineBasicBlock &MBB) {
}
bool SILoadStoreOptimizer::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
return false;
const TargetSubtargetInfo &STM = MF.getSubtarget();
TRI = static_cast<const SIRegisterInfo *>(STM.getRegisterInfo());
TII = static_cast<const SIInstrInfo *>(STM.getInstrInfo());

3
lib/Target/AMDGPU/SIShrinkInstructions.cpp
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@ -203,6 +203,9 @@ static bool isKImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) {
}
bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
return false;
MachineRegisterInfo &MRI = MF.getRegInfo();
const SIInstrInfo *TII =
static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());