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LR is in GPR, not tGPR even in Thumb1 mode.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104518 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2010-05-24 18:00:18 +00:00
parent a1132276e7
commit c7cf10c97e
2 changed files with 3 additions and 4 deletions
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5
lib/Target/ARM/ARMISelLowering.cpp
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@ -2158,10 +2158,7 @@ SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
} }
// Return LR, which contains the return address. Mark it an implicit live-in. // Return LR, which contains the return address. Mark it an implicit live-in.
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); unsigned Reg = MF.addLiveIn(ARM::LR, ARM::GPRRegisterClass);
TargetRegisterClass *RC = AFI->isThumb1OnlyFunction()
? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
unsigned Reg = MF.addLiveIn(ARM::LR, RC);
return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
} }

2
test/CodeGen/ARM/arm-returnaddr.ll
View File

@ -1,5 +1,7 @@
; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
; RUN: llc < %s -mtriple=thumbv6-apple-darwin
; rdar://8015977 ; rdar://8015977
; rdar://8020118
define arm_apcscc i8* @rt0(i32 %x) nounwind readnone { define arm_apcscc i8* @rt0(i32 %x) nounwind readnone {
entry: entry: