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Move pass configuration out of pass constructors: PostRAScheduler.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150096 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-02-08 21:22:53 +00:00
parent 61f1e3db43
commit c7d081b594
4 changed files with 11 additions and 9 deletions
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2
include/llvm/CodeGen/Passes.h
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@ -271,7 +271,7 @@ namespace llvm {
/// createPostRAScheduler - This pass performs post register allocation
/// scheduling.
FunctionPass *createPostRAScheduler(CodeGenOpt::Level OptLevel);
FunctionPass *createPostRAScheduler();
/// BranchFolding Pass - This pass performs machine code CFG based
/// optimizations to delete branches to branches, eliminate branches to

2
lib/CodeGen/Passes.cpp
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@ -285,7 +285,7 @@ void TargetPassConfig::addMachinePasses() {
// Second pass scheduler.
if (getOptLevel() != CodeGenOpt::None && !DisablePostRA) {
PM.add(createPostRAScheduler(getOptLevel()));
PM.add(createPostRAScheduler());
printNoVerify("After PostRAScheduler");
}

14
lib/CodeGen/PostRASchedulerList.cpp
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@ -82,16 +82,15 @@ namespace {
AliasAnalysis *AA;
const TargetInstrInfo *TII;
RegisterClassInfo RegClassInfo;
CodeGenOpt::Level OptLevel;
public:
static char ID;
PostRAScheduler(CodeGenOpt::Level ol) :
MachineFunctionPass(ID), OptLevel(ol) {}
PostRAScheduler() : MachineFunctionPass(ID) {}
void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<AliasAnalysis>();
AU.addRequired<TargetPassConfig>();
AU.addRequired<MachineDominatorTree>();
AU.addPreserved<MachineDominatorTree>();
AU.addRequired<MachineLoopInfo>();
@ -209,6 +208,8 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
AliasAnalysis *AA = &getAnalysis<AliasAnalysis>();
TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
RegClassInfo.runOnMachineFunction(Fn);
// Check for explicit enable/disable of post-ra scheduling.
@ -222,7 +223,8 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
// Check that post-RA scheduling is enabled for this target.
// This may upgrade the AntiDepMode.
const TargetSubtargetInfo &ST = Fn.getTarget().getSubtarget<TargetSubtargetInfo>();
if (!ST.enablePostRAScheduler(OptLevel, AntiDepMode, CriticalPathRCs))
if (!ST.enablePostRAScheduler(PassConfig->getOptLevel(), AntiDepMode,
CriticalPathRCs))
return false;
}
@ -710,6 +712,6 @@ void SchedulePostRATDList::ListScheduleTopDown() {
// Public Constructor Functions
//===----------------------------------------------------------------------===//
FunctionPass *llvm::createPostRAScheduler(CodeGenOpt::Level OptLevel) {
return new PostRAScheduler(OptLevel);
FunctionPass *llvm::createPostRAScheduler() {
return new PostRAScheduler();
}

2
lib/Target/PTX/PTXTargetMachine.cpp
View File

@ -353,7 +353,7 @@ bool PTXPassConfig::addCodeGenPasses(MCContext *&OutContext) {
// Second pass scheduler.
if (getOptLevel() != CodeGenOpt::None) {
PM.add(createPostRAScheduler(getOptLevel()));
PM.add(createPostRAScheduler());
printAndVerify("After PostRAScheduler");
}