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[X86] Add Requires[In64BitMode] around MOVSX64rr32/MOVSX64rm32. This makes it more strictly mutexed with the ARPL instruction 32-bit mode. Helps with some disassembler changes I'm experimenting with. Should be NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227962 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -139,11 +139,11 @@ def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
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def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
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"movs{lq|xd}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sext GR32:$src))], IIC_MOVSX>,
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Sched<[WriteALU]>;
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Sched<[WriteALU]>, Requires<[In64BitMode]>;
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def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
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"movs{lq|xd}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sextloadi64i32 addr:$src))], IIC_MOVSX>,
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Sched<[WriteALULd]>;
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Sched<[WriteALULd]>, Requires<[In64BitMode]>;
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// movzbq and movzwq encodings for the disassembler
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def MOVZX64rr8_Q : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src),
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