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[SystemZ] Check for presence of vector support in SystemZISelLowering

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A test case was found with llvm-stress that caused DAGCombiner to crash
when compiling for an older subtarget without vector support.

SystemZTargetLowering::combineTruncateExtract() should do nothing for older
subtargets.

This check was placed in canTreatAsByteVector(), which also helps in a few
other places.

Review: Ulrich Weigand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299763 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jonas Paulsson 2017-04-07 12:35:11 +00:00
parent 311a698548
commit c833eb7ff6
3 changed files with 24 additions and 2 deletions
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7
lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -4736,8 +4736,11 @@ const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
}
// Return true if VT is a vector whose elements are a whole number of bytes
// in width.
static bool canTreatAsByteVector(EVT VT) {
// in width. Also check for presence of vector support.
bool SystemZTargetLowering::canTreatAsByteVector(EVT VT) const {
if (!Subtarget.hasVector())
return false;
return VT.isVector() && VT.getScalarSizeInBits() % 8 == 0 && VT.isSimple();
}

1
lib/Target/SystemZ/SystemZISelLowering.h
View File

@ -537,6 +537,7 @@ private:
unsigned UnpackHigh) const;
SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
bool canTreatAsByteVector(EVT VT) const;
SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
unsigned Index, DAGCombinerInfo &DCI,
bool Force) const;

18
test/CodeGen/SystemZ/DAGCombine_trunc_extract.ll Normal file
View File

@ -0,0 +1,18 @@
; RUN: llc -mtriple=s390x-linux-gnu -mcpu=zEC12 < %s | FileCheck %s
;
; Check that DAGCombiner doesn't crash in SystemZ combineTruncateExtract()
; when handling EXTRACT_VECTOR_ELT without vector support.
define void @autogen_SD21598(<2 x i8> %Arg) {
; CHECK: stc %r3, 0(%r1)
; CHECK: j .LBB0_1
entry:
br label %loop
loop: ; preds = %CF249, %CF247
%Shuff = shufflevector <2 x i8> undef, <2 x i8> %Arg, <2 x i32> <i32 3, i32 1>
%E = extractelement <2 x i8> %Shuff, i32 0
store i8 %E, i8* undef
br label %loop
}