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More AVX2 instructions and their intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143895 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
5908536673
commit
c8eb880a7f
@ -1112,7 +1112,7 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty,
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llvm_v4f64_ty, llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx_vperm2f128_ps_256 :
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GCCBuiltin<"__builtin_ia32_vperm2f128_ps256">,
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GCCBuiltin<"_builtin_ia32_vperm2f128_ps256">,
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Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty,
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llvm_v8f32_ty, llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx_vperm2f128_si_256 :
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@ -1716,6 +1716,25 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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Intrinsic<[llvm_v4i64_ty], [llvm_v2i64_ty], [IntrNoMem]>;
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}
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// Vector permutation
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx2_permd : GCCBuiltin<"__builtin_ia32_permvarsi256">,
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Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty],
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[IntrNoMem]>;
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def int_x86_avx2_permq : GCCBuiltin<"__builtin_ia32_permdi256">,
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Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx2_permps : GCCBuiltin<"__builtin_ia32_permvarsf256">,
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Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty],
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[IntrNoMem]>;
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def int_x86_avx2_permpd : GCCBuiltin<"__builtin_ia32_permdf256">,
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Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx2_vperm2i128 : GCCBuiltin<"__builtin_ia32_permti256">,
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Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
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llvm_v4i64_ty, llvm_i8_ty], [IntrNoMem]>;
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}
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// Misc.
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx2_pmovmskb : GCCBuiltin<"__builtin_ia32_pmovmskb256">,
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@ -773,17 +773,20 @@ static int getID(struct InternalInstruction* insn) {
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if (insn->rexPrefix & 0x08)
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attrMask |= ATTR_REXW;
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if (getIDWithAttrMask(&instructionID, insn, attrMask))
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return -1;
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/* The following clauses compensate for limitations of the tables. */
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if ((attrMask & ATTR_VEXL) && (attrMask & ATTR_REXW)) {
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if ((attrMask & ATTR_VEXL) && (attrMask & ATTR_REXW) &&
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!(attrMask & ATTR_OPSIZE)) {
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/*
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* Some VEX instructions ignore the L-bit, but use the W-bit. Normally L-bit
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* has precedence since there are no L-bit with W-bit entries in the tables.
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* So if the L-bit isn't significant we should use the W-bit instead.
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* We only need to do this if the instruction doesn't specify OpSize since
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* there is a VEX_L_W_OPSIZE table.
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*/
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const struct InstructionSpecifier *spec;
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@ -111,7 +111,8 @@ enum attributeBits {
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ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \
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ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix")\
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ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix")\
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ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize")
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ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \
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ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize")
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#define ENUM_ENTRY(n, r, d) n,
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@ -460,7 +460,7 @@ class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, OpSize,
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Requires<[HasAVX2]>;
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class AVX2Ii8<bits<8> o, Format F, dag outs, dag ins, string asm,
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class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, OpSize,
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Requires<[HasAVX2]>;
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@ -7310,14 +7310,17 @@ def : Pat<(v4i64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
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//===----------------------------------------------------------------------===//
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// VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
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//
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let neverHasSideEffects = 1 in {
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def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, i8imm:$src3),
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"vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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[]>, VEX_4V;
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let mayLoad = 1 in
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def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, f256mem:$src2, i8imm:$src3),
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"vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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[]>, VEX_4V;
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}
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def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
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(VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
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@ -7402,18 +7405,18 @@ defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>;
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// AVX2 Instructions
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//===----------------------------------------------------------------------===//
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/// AVX2I_binop_rmi_int - AVX2 binary operator with 8-bit immediate
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multiclass AVX2I_binop_rmi_int<bits<8> opc, string OpcodeStr,
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/// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
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multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
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Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
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X86MemOperand x86memop> {
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let isCommutable = 1 in
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def rri : AVX2Ii8<opc, MRMSrcReg, (outs RC:$dst),
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def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, u32u8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
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VEX_4V;
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def rmi : AVX2Ii8<opc, MRMSrcMem, (outs RC:$dst),
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def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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@ -7424,10 +7427,10 @@ multiclass AVX2I_binop_rmi_int<bits<8> opc, string OpcodeStr,
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}
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let isCommutable = 0 in {
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defm VPBLENDD : AVX2I_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
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VR128, memopv16i8, i128mem>;
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defm VPBLENDDY : AVX2I_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
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VR256, memopv32i8, i256mem>;
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defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
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VR128, memopv16i8, i128mem>;
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defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
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VR256, memopv32i8, i256mem>;
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}
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//===----------------------------------------------------------------------===//
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@ -7465,3 +7468,62 @@ defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
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defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
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int_x86_avx2_pbroadcastq_128,
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int_x86_avx2_pbroadcastq_256>;
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//===----------------------------------------------------------------------===//
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// VPERM - Permute instructions
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//
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multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
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Intrinsic Int> {
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def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst, (Int VR256:$src1, VR256:$src2))]>, VEX_4V;
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def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, i256mem:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst, (Int VR256:$src1, (mem_frag addr:$src2)))]>,
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VEX_4V;
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}
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defm VPERMD : avx2_perm<0x36, "vpermd", memopv8i32, int_x86_avx2_permd>;
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defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, int_x86_avx2_permps>;
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multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
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Intrinsic Int> {
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def Yrr : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, i8imm:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst, (Int VR256:$src1, imm:$src2))]>, VEX;
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def Yrm : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
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(ins i256mem:$src1, i8imm:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst, (Int (mem_frag addr:$src1), imm:$src2))]>,
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VEX;
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}
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defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, int_x86_avx2_permq>,
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VEX_W;
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defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, int_x86_avx2_permpd>,
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VEX_W;
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//===----------------------------------------------------------------------===//
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// VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
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//
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def VPERM2I128rr : AVXAIi8<0x46, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, i8imm:$src3),
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"vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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[(set VR256:$dst,
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(int_x86_avx2_vperm2i128 VR256:$src1, VR256:$src2, imm:$src3))]>,
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VEX_4V;
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def VPERM2I128rm : AVXAIi8<0x46, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, f256mem:$src2, i8imm:$src3),
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"vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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[(set VR256:$dst,
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(int_x86_avx2_vperm2i128 VR256:$src1, (memopv4i64 addr:$src2),
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imm:$src3))]>,
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VEX_4V;
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@ -846,3 +846,43 @@ define <4 x i64> @test_x86_avx2_pbroadcastq_256(<2 x i64> %a0) {
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ret <4 x i64> %res
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}
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declare <4 x i64> @llvm.x86.avx2.pbroadcastq.256(<2 x i64>) nounwind readonly
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define <8 x i32> @test_x86_avx2_permd(<8 x i32> %a0, <8 x i32> %a1) {
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; CHECK: vpermd
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%res = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
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ret <8 x i32> %res
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}
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declare <8 x i32> @llvm.x86.avx2.permd(<8 x i32>, <8 x i32>) nounwind readonly
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define <8 x float> @test_x86_avx2_permps(<8 x float> %a0, <8 x float> %a1) {
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; CHECK: vpermps
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%res = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
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ret <8 x float> %res
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}
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declare <8 x float> @llvm.x86.avx2.permps(<8 x float>, <8 x float>) nounwind readonly
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define <4 x i64> @test_x86_avx2_permq(<4 x i64> %a0) {
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; CHECK: vpermq
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%res = call <4 x i64> @llvm.x86.avx2.permq(<4 x i64> %a0, i8 7) ; <<4 x i64>> [#uses=1]
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ret <4 x i64> %res
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}
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declare <4 x i64> @llvm.x86.avx2.permq(<4 x i64>, i8) nounwind readonly
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define <4 x double> @test_x86_avx2_permpd(<4 x double> %a0) {
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; CHECK: vpermpd
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%res = call <4 x double> @llvm.x86.avx2.permpd(<4 x double> %a0, i8 7) ; <<4 x double>> [#uses=1]
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ret <4 x double> %res
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}
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declare <4 x double> @llvm.x86.avx2.permpd(<4 x double>, i8) nounwind readonly
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define <4 x i64> @test_x86_avx2_vperm2i128(<4 x i64> %a0, <4 x i64> %a1) {
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; CHECK: vperm2i128
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%res = call <4 x i64> @llvm.x86.avx2.vperm2i128(<4 x i64> %a0, <4 x i64> %a1, i8 1) ; <<4 x i64>> [#uses=1]
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ret <4 x i64> %res
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}
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declare <4 x i64> @llvm.x86.avx2.vperm2i128(<4 x i64>, <4 x i64>, i8) nounwind readonly
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@ -95,7 +95,10 @@ static inline bool inheritsFrom(InstructionContext child,
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case IC_VEX_L:
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case IC_VEX_L_XS:
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case IC_VEX_L_XD:
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return false;
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case IC_VEX_L_OPSIZE:
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return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
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case IC_VEX_L_W_OPSIZE:
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return false;
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default:
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llvm_unreachable("Unknown instruction class");
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@ -494,7 +497,9 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, uint32_t &i) const {
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for (index = 0; index < 256; ++index) {
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o.indent(i * 2);
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if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
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if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
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o << "IC_VEX_L_W_OPSIZE";
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else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
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o << "IC_VEX_L_OPSIZE";
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else if ((index & ATTR_VEXL) && (index & ATTR_XD))
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o << "IC_VEX_L_XD";
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@ -285,9 +285,12 @@ InstructionContext RecognizableInstr::insnContext() const {
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InstructionContext insnContext;
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if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
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if (HasVEX_LPrefix && HasVEX_WPrefix)
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llvm_unreachable("Don't support VEX.L and VEX.W together");
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else if (HasOpSizePrefix && HasVEX_LPrefix)
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if (HasVEX_LPrefix && HasVEX_WPrefix) {
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if (HasOpSizePrefix)
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insnContext = IC_VEX_L_W_OPSIZE;
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else
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llvm_unreachable("Don't support VEX.L and VEX.W together");
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} else if (HasOpSizePrefix && HasVEX_LPrefix)
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insnContext = IC_VEX_L_OPSIZE;
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else if (HasOpSizePrefix && HasVEX_WPrefix)
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insnContext = IC_VEX_W_OPSIZE;
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