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[mips] Delete ArithOverflowR and ArithOverflow and use ArithLogicR and
ArithLogicI as the instruction base classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170642 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
6241703ee4
commit
c9e30ea42c
lib/Target/Mips
@ -83,26 +83,25 @@ let usesCustomInserter = 1, Predicates = [HasStdEnc],
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//===----------------------------------------------------------------------===//
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let DecoderNamespace = "Mips64" in {
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/// Arithmetic Instructions (ALU Immediate)
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def DADDi : ArithOverflowI<0x18, "daddi", add, simm16_64, immSExt16,
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CPU64Regs>;
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def DADDiu : ArithLogicI<0x19, "daddiu", add, simm16_64, immSExt16,
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CPU64Regs>, IsAsCheapAsAMove;
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def DANDi : ArithLogicI<0x0c, "andi", and, uimm16_64, immZExt16, CPU64Regs>;
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def DADDi : ArithLogicI<0x18, "daddi", simm16_64, immSExt16, CPU64Regs>;
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def DADDiu : ArithLogicI<0x19, "daddiu", simm16_64, immSExt16, CPU64Regs,
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add>, IsAsCheapAsAMove;
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def DANDi : ArithLogicI<0x0c, "andi", uimm16_64, immZExt16, CPU64Regs, and>;
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def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
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def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;
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def ORi64 : ArithLogicI<0x0d, "ori", or, uimm16_64, immZExt16, CPU64Regs>;
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def XORi64 : ArithLogicI<0x0e, "xori", xor, uimm16_64, immZExt16, CPU64Regs>;
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def ORi64 : ArithLogicI<0x0d, "ori", uimm16_64, immZExt16, CPU64Regs, or>;
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def XORi64 : ArithLogicI<0x0e, "xori", uimm16_64, immZExt16, CPU64Regs, xor>;
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def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>;
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/// Arithmetic Instructions (3-Operand, R-Type)
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def DADD : ArithOverflowR<0x00, 0x2C, "dadd", IIAlu, CPU64Regs, 1>;
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def DADDu : ArithLogicR<0x00, 0x2d, "daddu", add, IIAlu, CPU64Regs, 1>;
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def DSUBu : ArithLogicR<0x00, 0x2f, "dsubu", sub, IIAlu, CPU64Regs>;
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def DADD : ArithLogicR<0x00, 0x2C, "dadd", IIAlu, CPU64Regs, 1>;
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def DADDu : ArithLogicR<0x00, 0x2d, "daddu", IIAlu, CPU64Regs, 1, add>;
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def DSUBu : ArithLogicR<0x00, 0x2f, "dsubu", IIAlu, CPU64Regs, 0, sub>;
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def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>;
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def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>;
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def AND64 : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPU64Regs, 1>;
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def OR64 : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPU64Regs, 1>;
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def XOR64 : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPU64Regs, 1>;
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def AND64 : ArithLogicR<0x00, 0x24, "and", IIAlu, CPU64Regs, 1, and>;
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def OR64 : ArithLogicR<0x00, 0x25, "or", IIAlu, CPU64Regs, 1, or>;
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def XOR64 : ArithLogicR<0x00, 0x26, "xor", IIAlu, CPU64Regs, 1, xor>;
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def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>;
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/// Shift Instructions
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@ -345,8 +345,9 @@ def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel),
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def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
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// Arithmetic and logical instructions with 3 register operands.
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class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
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InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
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class ArithLogicR<bits<6> op, bits<6> func, string instr_asm,
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InstrItinClass itin, RegisterClass RC, bit isComm = 0,
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SDPatternOperator OpNode = null_frag>:
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FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
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!strconcat(instr_asm, "\t$rd, $rs, $rt"),
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[(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> {
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@ -355,28 +356,15 @@ class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
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let isReMaterializable = 1;
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}
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class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
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InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
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FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
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!strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> {
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let shamt = 0;
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let isCommutable = isComm;
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}
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// Arithmetic and logical instructions with 2 register operands.
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class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode,
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Operand Od, PatLeaf imm_type, RegisterClass RC> :
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class ArithLogicI<bits<6> op, string instr_asm, Operand Od, PatLeaf imm_type,
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RegisterClass RC, SDPatternOperator OpNode = null_frag> :
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FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
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!strconcat(instr_asm, "\t$rt, $rs, $imm16"),
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[(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu> {
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let isReMaterializable = 1;
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}
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class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
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Operand Od, PatLeaf imm_type, RegisterClass RC> :
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FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
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!strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>;
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// Arithmetic Multiply ADD/SUB
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let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
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class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
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@ -931,26 +919,26 @@ def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>;
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//===----------------------------------------------------------------------===//
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/// Arithmetic Instructions (ALU Immediate)
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def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>,
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def ADDiu : ArithLogicI<0x09, "addiu", simm16, immSExt16, CPURegs, add>,
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IsAsCheapAsAMove;
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def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>;
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def ADDi : ArithLogicI<0x08, "addi", simm16, immSExt16, CPURegs>;
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def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
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def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
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def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>;
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def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>;
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def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>;
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def ANDi : ArithLogicI<0x0c, "andi", uimm16, immZExt16, CPURegs, and>;
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def ORi : ArithLogicI<0x0d, "ori", uimm16, immZExt16, CPURegs, or>;
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def XORi : ArithLogicI<0x0e, "xori", uimm16, immZExt16, CPURegs, xor>;
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def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>;
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/// Arithmetic Instructions (3-Operand, R-Type)
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def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>;
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def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>;
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def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
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def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>;
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def ADDu : ArithLogicR<0x00, 0x21, "addu", IIAlu, CPURegs, 1, add>;
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def SUBu : ArithLogicR<0x00, 0x23, "subu", IIAlu, CPURegs, 0, sub>;
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def ADD : ArithLogicR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
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def SUB : ArithLogicR<0x00, 0x22, "sub", IIAlu, CPURegs, 0>;
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def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
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def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
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def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>;
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def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>;
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def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>;
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def AND : ArithLogicR<0x00, 0x24, "and", IIAlu, CPURegs, 1, and>;
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def OR : ArithLogicR<0x00, 0x25, "or", IIAlu, CPURegs, 1, or>;
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def XOR : ArithLogicR<0x00, 0x26, "xor", IIAlu, CPURegs, 1, xor>;
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def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>;
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/// Shift Instructions
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@ -1075,7 +1063,7 @@ def MSUBU : MArithR<5, "msubu", MipsMSubu>;
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// MUL is a assembly macro in the current used ISAs. In recent ISA's
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// it is a real instruction.
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def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
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def MUL : ArithLogicR<0x1c, 0x02, "mul", IIImul, CPURegs, 1, mul>,
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Requires<[HasStdEnc]>;
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def RDHWR : ReadHardware<CPURegs, HWRegs>;
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