RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2025-03-03 02:17:41 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[ARM][FastISel] Use TST #1 instead of CMP #0 for select.

Browse Source 
Since r234249, i1 are sext instead of zext; because of that, doing
"CMP rN, #0; IT EQ/NE" isn't correct anymore.

"TST #1" is the conservatively correct alternative - the tradeoff being
that it doesn't have a 16-bit encoding -, so use that instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236569 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ahmed Bougacha 2015-05-06 04:14:02 +00:00
parent 5a8a366ddf
commit caa560cfb9
2 changed files with 16 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/ARM/ARMFastISel.cpp
View File

@ -1657,12 +1657,12 @@ bool ARMFastISel::SelectSelect(const Instruction *I) {
if (Op2Reg == 0) return false;
}
unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;
CondReg = constrainOperandRegClass(TII.get(CmpOpc), CondReg, 0);
unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0);
AddOptionalDefs(
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
.addReg(CondReg)
.addImm(0));
.addImm(1));
unsigned MovCCOpc;
const TargetRegisterClass *RC;

24
test/CodeGen/ARM/fast-isel-select.ll
View File

@ -7,12 +7,12 @@ define i32 @t1(i1 %c) nounwind readnone {
entry:
; ARM: t1
; ARM: movw r{{[1-9]}}, #10
; ARM: cmp r0, #0
; ARM: tst r0, #1
; ARM: moveq r{{[1-9]}}, #20
; ARM: mov r0, r{{[1-9]}}
; THUMB: t1
; THUMB: movs r{{[1-9]}}, #10
; THUMB: cmp r0, #0
; THUMB: tst.w r0, #1
; THUMB: it eq
; THUMB: moveq r{{[1-9]}}, #20
; THUMB: mov r0, r{{[1-9]}}
@ -23,11 +23,11 @@ entry:
define i32 @t2(i1 %c, i32 %a) nounwind readnone {
entry:
; ARM: t2
; ARM: cmp r0, #0
; ARM: tst r0, #1
; ARM: moveq r{{[1-9]}}, #20
; ARM: mov r0, r{{[1-9]}}
; THUMB: t2
; THUMB: cmp r0, #0
; THUMB: tst.w r0, #1
; THUMB: it eq
; THUMB: moveq r{{[1-9]}}, #20
; THUMB: mov r0, r{{[1-9]}}
@ -38,11 +38,11 @@ entry:
define i32 @t3(i1 %c, i32 %a, i32 %b) nounwind readnone {
entry:
; ARM: t3
; ARM: cmp r0, #0
; ARM: tst r0, #1
; ARM: movne r2, r1
; ARM: add r0, r2, r1
; THUMB: t3
; THUMB: cmp r0, #0
; THUMB: tst.w r0, #1
; THUMB: it ne
; THUMB: movne r2, r1
; THUMB: add.w r0, r2, r1
@ -55,12 +55,12 @@ define i32 @t4(i1 %c) nounwind readnone {
entry:
; ARM: t4
; ARM: mvn r{{[1-9]}}, #9
; ARM: cmp r0, #0
; ARM: tst r0, #1
; ARM: mvneq r{{[1-9]}}, #0
; ARM: mov r0, r{{[1-9]}}
; THUMB-LABEL: t4
; THUMB: mvn [[REG:r[1-9]+]], #9
; THUMB: cmp r0, #0
; THUMB: tst.w r0, #1
; THUMB: it eq
; THUMB: mvneq [[REG]], #0
; THUMB: mov r0, [[REG]]
@ -71,11 +71,11 @@ entry:
define i32 @t5(i1 %c, i32 %a) nounwind readnone {
entry:
; ARM: t5
; ARM: cmp r0, #0
; ARM: tst r0, #1
; ARM: mvneq r{{[1-9]}}, #1
; ARM: mov r0, r{{[1-9]}}
; THUMB: t5
; THUMB: cmp r0, #0
; THUMB: tst.w r0, #1
; THUMB: it eq
; THUMB: mvneq r{{[1-9]}}, #1
; THUMB: mov r0, r{{[1-9]}}
@ -87,11 +87,11 @@ entry:
define i32 @t6(i1 %c, i32 %a) nounwind readnone {
entry:
; ARM: t6
; ARM: cmp r0, #0
; ARM: tst r0, #1
; ARM: mvneq r{{[1-9]}}, #978944
; ARM: mov r0, r{{[1-9]}}
; THUMB: t6
; THUMB: cmp r0, #0
; THUMB: tst.w r0, #1
; THUMB: it eq
; THUMB: mvneq r{{[1-9]}}, #978944
; THUMB: mov r0, r{{[1-9]}}