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[InstCombine] fix tests for adjusted min/max

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1. Delete identical tests
2. Rename tests to reflect actual functionality
3. Add comments
4. Add unsigned variants
5. Add vector variants with FIXME comments
6. Rename test file


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285699 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel 2016-11-01 15:48:30 +00:00
parent cf8d4833fd
commit caa8396841
2 changed files with 273 additions and 181 deletions
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273
test/Transforms/InstCombine/adjust-for-minmax.ll Normal file
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@ -0,0 +1,273 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
; Instcombine should recognize that this code can be adjusted to fit the canonical max/min pattern.
; No change
define i32 @smax1(i32 %n) {
; CHECK-LABEL: @smax1(
; CHECK-NEXT: [[T:%.*]] = icmp sgt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 %n, i32 0
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sgt i32 %n, 0
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
; No change
define i32 @smin1(i32 %n) {
; CHECK-LABEL: @smin1(
; CHECK-NEXT: [[T:%.*]] = icmp slt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 %n, i32 0
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp slt i32 %n, 0
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
; Canonicalize icmp predicate.
define i32 @smax2(i32 %n) {
; CHECK-LABEL: @smax2(
; CHECK-NEXT: [[T:%.*]] = icmp sgt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 %n, i32 0
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sge i32 %n, 1
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
; Canonicalize icmp predicate.
define i32 @smin2(i32 %n) {
; CHECK-LABEL: @smin2(
; CHECK-NEXT: [[T:%.*]] = icmp slt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 %n, i32 0
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sle i32 %n, -1
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
; Swap signed pred and select ops.
define i32 @smax3(i32 %n) {
; CHECK-LABEL: @smax3(
; CHECK-NEXT: [[T:%.*]] = icmp slt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 0, i32 %n
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sgt i32 %n, -1
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
; FIXME
; Swap vector signed pred and select ops.
define <2 x i32> @smax3_vec(<2 x i32> %n) {
; CHECK-LABEL: @smax3_vec(
; CHECK-NEXT: [[T:%.*]] = icmp sgt <2 x i32> %n, <i32 -1, i32 -1>
; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp sgt <2 x i32> %n, <i32 -1, i32 -1>
%m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> zeroinitializer
ret <2 x i32> %m
}
; Swap signed pred and select ops.
define i32 @smin3(i32 %n) {
; CHECK-LABEL: @smin3(
; CHECK-NEXT: [[T:%.*]] = icmp sgt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 0, i32 %n
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp slt i32 %n, 1
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
; FIXME
; Swap vector signed pred and select ops.
define <2 x i32> @smin3_vec(<2 x i32> %n) {
; CHECK-LABEL: @smin3_vec(
; CHECK-NEXT: [[T:%.*]] = icmp slt <2 x i32> %n, <i32 1, i32 1>
; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp slt <2 x i32> %n, <i32 1, i32 1>
%m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> zeroinitializer
ret <2 x i32> %m
}
; Swap unsigned pred and select ops.
define i32 @umax3(i32 %n) {
; CHECK-LABEL: @umax3(
; CHECK-NEXT: [[T:%.*]] = icmp ult i32 %n, 5
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 5, i32 %n
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp ugt i32 %n, 4
%m = select i1 %t, i32 %n, i32 5
ret i32 %m
}
; FIXME
; Swap vector unsigned pred and select ops.
define <2 x i32> @umax3_vec(<2 x i32> %n) {
; CHECK-LABEL: @umax3_vec(
; CHECK-NEXT: [[T:%.*]] = icmp ugt <2 x i32> %n, <i32 4, i32 4>
; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> <i32 5, i32 5>
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp ugt <2 x i32> %n, <i32 4, i32 4>
%m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> <i32 5, i32 5>
ret <2 x i32> %m
}
; Swap unsigned pred and select ops.
define i32 @umin3(i32 %n) {
; CHECK-LABEL: @umin3(
; CHECK-NEXT: [[T:%.*]] = icmp ugt i32 %n, 6
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 6, i32 %n
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp ult i32 %n, 7
%m = select i1 %t, i32 %n, i32 6
ret i32 %m
}
; FIXME
; Swap vector unsigned pred and select ops.
define <2 x i32> @umin3_vec(<2 x i32> %n) {
; CHECK-LABEL: @umin3_vec(
; CHECK-NEXT: [[T:%.*]] = icmp ult <2 x i32> %n, <i32 7, i32 7>
; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> <i32 6, i32 6>
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp ult <2 x i32> %n, <i32 7, i32 7>
%m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> <i32 6, i32 6>
ret <2 x i32> %m
}
; Canonicalize signed pred and swap pred and select ops.
define i32 @smax4(i32 %n) {
; CHECK-LABEL: @smax4(
; CHECK-NEXT: [[T:%.*]] = icmp slt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 0, i32 %n
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sge i32 %n, 0
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
; FIXME
; Canonicalize vector signed pred and swap pred and select ops.
define <2 x i32> @smax4_vec(<2 x i32> %n) {
; CHECK-LABEL: @smax4_vec(
; CHECK-NEXT: [[T:%.*]] = icmp sgt <2 x i32> %n, <i32 -1, i32 -1>
; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp sge <2 x i32> %n, zeroinitializer
%m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> zeroinitializer
ret <2 x i32> %m
}
; Canonicalize signed pred and swap pred and select ops.
define i32 @smin4(i32 %n) {
; CHECK-LABEL: @smin4(
; CHECK-NEXT: [[T:%.*]] = icmp sgt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 0, i32 %n
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sle i32 %n, 0
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
; FIXME
; Canonicalize vector signed pred and swap pred and select ops.
define <2 x i32> @smin4_vec(<2 x i32> %n) {
; CHECK-LABEL: @smin4_vec(
; CHECK-NEXT: [[T:%.*]] = icmp slt <2 x i32> %n, <i32 1, i32 1>
; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp sle <2 x i32> %n, zeroinitializer
%m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> zeroinitializer
ret <2 x i32> %m
}
; Canonicalize unsigned pred and swap pred and select ops.
define i32 @umax4(i32 %n) {
; CHECK-LABEL: @umax4(
; CHECK-NEXT: [[T:%.*]] = icmp ult i32 %n, 8
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 8, i32 %n
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp uge i32 %n, 8
%m = select i1 %t, i32 %n, i32 8
ret i32 %m
}
; FIXME
; Canonicalize vector unsigned pred and swap pred and select ops.
define <2 x i32> @umax4_vec(<2 x i32> %n) {
; CHECK-LABEL: @umax4_vec(
; CHECK-NEXT: [[T:%.*]] = icmp ugt <2 x i32> %n, <i32 7, i32 7>
; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> <i32 8, i32 8>
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp uge <2 x i32> %n, <i32 8, i32 8>
%m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> <i32 8, i32 8>
ret <2 x i32> %m
}
; Canonicalize unsigned pred and swap pred and select ops.
define i32 @umin4(i32 %n) {
; CHECK-LABEL: @umin4(
; CHECK-NEXT: [[T:%.*]] = icmp ugt i32 %n, 9
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 9, i32 %n
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp ule i32 %n, 9
%m = select i1 %t, i32 %n, i32 9
ret i32 %m
}
; FIXME
; Canonicalize vector unsigned pred and swap pred and select ops.
define <2 x i32> @umin4_vec(<2 x i32> %n) {
; CHECK-LABEL: @umin4_vec(
; CHECK-NEXT: [[T:%.*]] = icmp ult <2 x i32> %n, <i32 10, i32 10>
; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> <i32 9, i32 9>
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp ule <2 x i32> %n, <i32 9, i32 9>
%m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> <i32 9, i32 9>
ret <2 x i32> %m
}

181
test/Transforms/InstCombine/adjust-for-sminmax.ll
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@ -1,181 +0,0 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
; Instcombine should recognize that this code can be adjusted
; to fit the canonical smax/smin pattern.
define i32 @floor_a(i32 %n) {
; CHECK-LABEL: @floor_a(
; CHECK-NEXT: [[T:%.*]] = icmp slt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 0, i32 %n
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sgt i32 %n, -1
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
define i32 @ceil_a(i32 %n) {
; CHECK-LABEL: @ceil_a(
; CHECK-NEXT: [[T:%.*]] = icmp sgt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 0, i32 %n
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp slt i32 %n, 1
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
define i32 @floor_b(i32 %n) {
; CHECK-LABEL: @floor_b(
; CHECK-NEXT: [[T:%.*]] = icmp sgt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 %n, i32 0
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sgt i32 %n, 0
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
define i32 @ceil_b(i32 %n) {
; CHECK-LABEL: @ceil_b(
; CHECK-NEXT: [[T:%.*]] = icmp slt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 %n, i32 0
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp slt i32 %n, 0
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
define i32 @floor_c(i32 %n) {
; CHECK-LABEL: @floor_c(
; CHECK-NEXT: [[T:%.*]] = icmp slt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 0, i32 %n
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sge i32 %n, 0
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
define i32 @ceil_c(i32 %n) {
; CHECK-LABEL: @ceil_c(
; CHECK-NEXT: [[T:%.*]] = icmp sgt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 0, i32 %n
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sle i32 %n, 0
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
define i32 @floor_d(i32 %n) {
; CHECK-LABEL: @floor_d(
; CHECK-NEXT: [[T:%.*]] = icmp sgt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 %n, i32 0
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sge i32 %n, 1
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
define i32 @ceil_d(i32 %n) {
; CHECK-LABEL: @ceil_d(
; CHECK-NEXT: [[T:%.*]] = icmp slt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 %n, i32 0
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sle i32 %n, -1
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
define i32 @floor_e(i32 %n) {
; CHECK-LABEL: @floor_e(
; CHECK-NEXT: [[T:%.*]] = icmp slt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 0, i32 %n
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sgt i32 %n, -1
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
define i32 @ceil_e(i32 %n) {
; CHECK-LABEL: @ceil_e(
; CHECK-NEXT: [[T:%.*]] = icmp sgt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 0, i32 %n
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp slt i32 %n, 1
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
define i32 @floor_f(i32 %n) {
; CHECK-LABEL: @floor_f(
; CHECK-NEXT: [[T:%.*]] = icmp sgt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 %n, i32 0
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sgt i32 %n, 0
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
define i32 @ceil_f(i32 %n) {
; CHECK-LABEL: @ceil_f(
; CHECK-NEXT: [[T:%.*]] = icmp slt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 %n, i32 0
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp slt i32 %n, 0
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
define i32 @floor_g(i32 %n) {
; CHECK-LABEL: @floor_g(
; CHECK-NEXT: [[T:%.*]] = icmp slt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 0, i32 %n
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sge i32 %n, 0
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
define i32 @ceil_g(i32 %n) {
; CHECK-LABEL: @ceil_g(
; CHECK-NEXT: [[T:%.*]] = icmp sgt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 0, i32 %n
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sle i32 %n, 0
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
define i32 @floor_h(i32 %n) {
; CHECK-LABEL: @floor_h(
; CHECK-NEXT: [[T:%.*]] = icmp sgt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 %n, i32 0
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sge i32 %n, 1
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}
define i32 @ceil_h(i32 %n) {
; CHECK-LABEL: @ceil_h(
; CHECK-NEXT: [[T:%.*]] = icmp slt i32 %n, 0
; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 %n, i32 0
; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sle i32 %n, -1
%m = select i1 %t, i32 %n, i32 0
ret i32 %m
}