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Spelling mistakes in comments. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299069 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3664,7 +3664,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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if (VA.isRegLoc()) {
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if (VA.needsCustom()) {
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assert((CallConv == CallingConv::X86_RegCall) &&
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"Expecting custome case only in regcall calling convention");
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"Expecting custom case only in regcall calling convention");
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// This means that we are in special case where one argument was
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// passed through two register locations - Skip the next location
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++I;
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@ -9362,7 +9362,7 @@ static SDValue lowerVectorShuffleWithSSE4A(const SDLoc &DL, MVT VT, SDValue V1,
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/// Given a specific number of elements, element bit width, and extension
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/// stride, produce either a zero or any extension based on the available
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/// features of the subtarget. The extended elements are consecutive and
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/// begin and can start from an offseted element index in the input; to
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/// begin and can start from an offsetted element index in the input; to
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/// avoid excess shuffling the offset must either being in the bottom lane
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/// or at the start of a higher lane. All extended elements must be from
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/// the same lane.
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@ -9402,7 +9402,7 @@ static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
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// Found a valid zext mask! Try various lowering strategies based on the
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// input type and available ISA extensions.
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if (Subtarget.hasSSE41()) {
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// Not worth offseting 128-bit vectors if scale == 2, a pattern using
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// Not worth offsetting 128-bit vectors if scale == 2, a pattern using
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// PUNPCK will catch this in a later shuffle match.
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if (Offset && Scale == 2 && VT.is128BitVector())
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return SDValue();
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@ -10736,7 +10736,7 @@ static SDValue lowerV4I32VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask,
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// We implement this with SHUFPS because it can blend from two vectors.
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// Because we're going to eventually use SHUFPS, we use SHUFPS even to build
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// up the inputs, bypassing domain shift penalties that we would encur if we
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// up the inputs, bypassing domain shift penalties that we would incur if we
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// directly used PSHUFD on Nehalem and older. For newer chips, this isn't
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// relevant.
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SDValue CastV1 = DAG.getBitcast(MVT::v4f32, V1);
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@ -10767,7 +10767,7 @@ static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
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assert(VT.getVectorElementType() == MVT::i16 && "Bad input type!");
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MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
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assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
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assert(Mask.size() == 8 && "Shuffle mask length doesn't match!");
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MutableArrayRef<int> LoMask = Mask.slice(0, 4);
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MutableArrayRef<int> HiMask = Mask.slice(4, 4);
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@ -11573,7 +11573,7 @@ static SDValue lowerV16I8VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask,
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PostDupI16Shuffle[i / 2] = MappedMask;
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else
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assert(PostDupI16Shuffle[i / 2] == MappedMask &&
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"Conflicting entrties in the original shuffle!");
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"Conflicting entries in the original shuffle!");
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}
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return DAG.getBitcast(
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MVT::v16i8,
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@ -14450,7 +14450,7 @@ unsigned X86TargetLowering::getGlobalWrapperKind(const GlobalValue *GV) const {
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}
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// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
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// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
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// their target counterpart wrapped in the X86ISD::Wrapper node. Suppose N is
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// one of the above mentioned nodes. It has to be wrapped because otherwise
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// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
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// be used to form addressing mode. These wrapped nodes will be selected
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@ -14826,7 +14826,7 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
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Subtarget.isTargetWindowsItanium() ||
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Subtarget.isTargetWindowsGNU()) {
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// Just use the implicit TLS architecture
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// Need to generate someting similar to:
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// Need to generate something similar to:
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// mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
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// ; from TEB
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// mov ecx, dword [rel _tls_index]: Load index (from C runtime)
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@ -15907,7 +15907,7 @@ SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
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}
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if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
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// On AVX2, v8i32 -> v8i16 becomed PSHUFB.
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// On AVX2, v8i32 -> v8i16 becomes PSHUFB.
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if (Subtarget.hasInt256()) {
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In = DAG.getBitcast(MVT::v32i8, In);
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@ -16727,7 +16727,7 @@ SDValue X86TargetLowering::getRecipEstimate(SDValue Op, SelectionDAG &DAG,
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}
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/// If we have at least two divisions that use the same divisor, convert to
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/// multplication by a reciprocal. This may need to be adjusted for a given
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/// multiplication by a reciprocal. This may need to be adjusted for a given
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/// CPU if a division's cost is not at least twice the cost of a multiplication.
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/// This is because we still need one division to calculate the reciprocal and
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/// then we need two multiplies by that reciprocal as replacements for the
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@ -22965,7 +22965,7 @@ static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, const SDLoc &DL,
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// index into a in-register pre-computed pop count table. We then split up the
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// input vector in two new ones: (1) a vector with only the shifted-right
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// higher nibbles for each byte and (2) a vector with the lower nibbles (and
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// masked out higher ones) for each byte. PSHUB is used separately with both
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// masked out higher ones) for each byte. PSHUFB is used separately with both
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// to index the in-register table. Next, both are added and the result is a
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// i8 vector where each element contains the pop count for input byte.
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//
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@ -23582,7 +23582,7 @@ static SDValue LowerMLOAD(SDValue Op, const X86Subtarget &Subtarget,
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// Mask element has to be i1.
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MVT MaskEltTy = Mask.getSimpleValueType().getScalarType();
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assert((MaskEltTy == MVT::i1 || VT.getVectorNumElements() <= 4) &&
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"We handle 4x32, 4x64 and 2x64 vectors only in this casse");
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"We handle 4x32, 4x64 and 2x64 vectors only in this case");
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MVT WideMaskVT = MVT::getVectorVT(MaskEltTy, NumEltsInWideVec);
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@ -23638,7 +23638,7 @@ static SDValue LowerMSTORE(SDValue Op, const X86Subtarget &Subtarget,
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// Mask element has to be i1.
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MVT MaskEltTy = Mask.getSimpleValueType().getScalarType();
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assert((MaskEltTy == MVT::i1 || VT.getVectorNumElements() <= 4) &&
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"We handle 4x32, 4x64 and 2x64 vectors only in this casse");
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"We handle 4x32, 4x64 and 2x64 vectors only in this case");
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MVT WideMaskVT = MVT::getVectorVT(MaskEltTy, NumEltsInWideVec);
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@ -23698,7 +23698,7 @@ static SDValue LowerMGATHER(SDValue Op, const X86Subtarget &Subtarget,
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Mask = ExtendToType(Mask, ExtMaskVT, DAG, true);
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Mask = DAG.getNode(ISD::TRUNCATE, dl, MaskBitVT, Mask);
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// The pass-thru value
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// The pass-through value
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MVT NewVT = MVT::getVectorVT(VT.getScalarType(), NumElts);
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Src0 = ExtendToType(Src0, NewVT, DAG);
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@ -25391,7 +25391,7 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr &MI,
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//
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// (CMOV (CMOV F, T, cc1), T, cc2)
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//
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// to two successives branches. For that, we look for another CMOV as the
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// to two successive branches. For that, we look for another CMOV as the
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// following instruction.
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//
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// Without this, we would add a PHI between the two jumps, which ends up
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