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AMDGPU : Add a function to enable and disable IEEEBit for SC and shader

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respectively.

Differential Revision: http://reviews.llvm.org/D25789

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284655 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Wei Ding 2016-10-19 22:34:49 +00:00
parent 599a7aa9a7
commit cc8ca50286
4 changed files with 45 additions and 13 deletions
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2
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
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@ -548,7 +548,7 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
// register.
ProgInfo.FloatMode = getFPMode(MF);
ProgInfo.IEEEMode = 0;
ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
// Make clamp modifier on NaN input returns 0.
ProgInfo.DX10Clamp = 1;

4
lib/Target/AMDGPU/AMDGPUSubtarget.h
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@ -249,6 +249,10 @@ public:
return DumpCode;
}
bool enableIEEEBit(const MachineFunction &MF) const {
return AMDGPU::isCompute(MF.getFunction()->getCallingConv());
}
/// Return the amount of LDS that can be used that will not restrict the
/// occupancy lower than WaveCount.
unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount) const;

40
test/CodeGen/AMDGPU/default-fp-mode.ll
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@ -2,7 +2,7 @@
; GCN-LABEL: {{^}}test_default_si:
; GCN: FloatMode: 192
; GCN: IeeeMode: 0
; GCN: IeeeMode: 1
define void @test_default_si(float addrspace(1)* %out0, double addrspace(1)* %out1) #0 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
@ -11,7 +11,7 @@ define void @test_default_si(float addrspace(1)* %out0, double addrspace(1)* %ou
; GCN-LABEL: {{^}}test_default_vi:
; GCN: FloatMode: 192
; GCN: IeeeMode: 0
; GCN: IeeeMode: 1
define void @test_default_vi(float addrspace(1)* %out0, double addrspace(1)* %out1) #1 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
@ -20,7 +20,7 @@ define void @test_default_vi(float addrspace(1)* %out0, double addrspace(1)* %ou
; GCN-LABEL: {{^}}test_f64_denormals:
; GCN: FloatMode: 192
; GCN: IeeeMode: 0
; GCN: IeeeMode: 1
define void @test_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #2 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
@ -29,7 +29,7 @@ define void @test_f64_denormals(float addrspace(1)* %out0, double addrspace(1)*
; GCN-LABEL: {{^}}test_f32_denormals:
; GCNL: FloatMode: 48
; GCN: IeeeMode: 0
; GCN: IeeeMode: 1
define void @test_f32_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #3 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
@ -38,7 +38,7 @@ define void @test_f32_denormals(float addrspace(1)* %out0, double addrspace(1)*
; GCN-LABEL: {{^}}test_f32_f64_denormals:
; GCN: FloatMode: 240
; GCN: IeeeMode: 0
; GCN: IeeeMode: 1
define void @test_f32_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #4 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
@ -47,13 +47,41 @@ define void @test_f32_f64_denormals(float addrspace(1)* %out0, double addrspace(
; GCN-LABEL: {{^}}test_no_denormals
; GCN: FloatMode: 0
; GCN: IeeeMode: 0
; GCN: IeeeMode: 1
define void @test_no_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #5 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
ret void
}
; GCN-LABEL: {{^}}kill_gs_const:
; GCN: IeeeMode: 0
define amdgpu_gs void @kill_gs_const() {
main_body:
%0 = icmp ule i32 0, 3
%1 = select i1 %0, float 1.000000e+00, float -1.000000e+00
call void @llvm.AMDGPU.kill(float %1)
%2 = icmp ule i32 3, 0
%3 = select i1 %2, float 1.000000e+00, float -1.000000e+00
call void @llvm.AMDGPU.kill(float %3)
ret void
}
; GCN-LABEL: {{^}}kill_vcc_implicit_def:
; GCN: IeeeMode: 0
define amdgpu_ps void @kill_vcc_implicit_def([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) {
entry:
%tmp0 = fcmp olt float %13, 0.0
call void @llvm.AMDGPU.kill(float %14)
%tmp1 = select i1 %tmp0, float 1.0, float 0.0
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 1, i32 1, float %tmp1, float %tmp1, float %tmp1, float %tmp1)
ret void
}
declare void @llvm.AMDGPU.kill(float)
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
attributes #0 = { nounwind "target-cpu"="tahiti" }
attributes #1 = { nounwind "target-cpu"="fiji" }
attributes #2 = { nounwind "target-features"="+fp64-denormals" }

12
test/CodeGen/AMDGPU/hsa-fp-mode.ll
View File

@ -3,7 +3,7 @@
; GCN-LABEL: {{^}}test_default_ci:
; GCN: float_mode = 192
; GCN: enable_dx10_clamp = 1
; GCN: enable_ieee_mode = 0
; GCN: enable_ieee_mode = 1
define void @test_default_ci(float addrspace(1)* %out0, double addrspace(1)* %out1) #0 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
@ -13,7 +13,7 @@ define void @test_default_ci(float addrspace(1)* %out0, double addrspace(1)* %ou
; GCN-LABEL: {{^}}test_default_vi:
; GCN: float_mode = 192
; GCN: enable_dx10_clamp = 1
; GCN: enable_ieee_mode = 0
; GCN: enable_ieee_mode = 1
define void @test_default_vi(float addrspace(1)* %out0, double addrspace(1)* %out1) #1 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
@ -23,7 +23,7 @@ define void @test_default_vi(float addrspace(1)* %out0, double addrspace(1)* %ou
; GCN-LABEL: {{^}}test_f64_denormals:
; GCN: float_mode = 192
; GCN: enable_dx10_clamp = 1
; GCN: enable_ieee_mode = 0
; GCN: enable_ieee_mode = 1
define void @test_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #2 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
@ -33,7 +33,7 @@ define void @test_f64_denormals(float addrspace(1)* %out0, double addrspace(1)*
; GCN-LABEL: {{^}}test_f32_denormals:
; GCN: float_mode = 48
; GCN: enable_dx10_clamp = 1
; GCN: enable_ieee_mode = 0
; GCN: enable_ieee_mode = 1
define void @test_f32_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #3 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
@ -43,7 +43,7 @@ define void @test_f32_denormals(float addrspace(1)* %out0, double addrspace(1)*
; GCN-LABEL: {{^}}test_f32_f64_denormals:
; GCN: float_mode = 240
; GCN: enable_dx10_clamp = 1
; GCN: enable_ieee_mode = 0
; GCN: enable_ieee_mode = 1
define void @test_f32_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #4 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
@ -53,7 +53,7 @@ define void @test_f32_f64_denormals(float addrspace(1)* %out0, double addrspace(
; GCN-LABEL: {{^}}test_no_denormals:
; GCN: float_mode = 0
; GCN: enable_dx10_clamp = 1
; GCN: enable_ieee_mode = 0
; GCN: enable_ieee_mode = 1
define void @test_no_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #5 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1