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CodeGen: Avoid iterator conversions in TwoAddressInstructionPass, NFC

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Mostly through preferring MachineInstr&, avoid implicit conversions from
iterator to pointer.

Although this may bitrot (since there are other uses blocking me from
removing the implicit operator), this removes the last of the implicit
conversions from MachineInstrBundleIterator to MachineInstr* in the
LLVMCodeGen build target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274893 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan P. N. Exon Smith 2016-07-08 17:43:08 +00:00
parent fccaf97f84
commit ccb7a2f240
1 changed files with 51 additions and 55 deletions
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106
lib/CodeGen/TwoAddressInstructionPass.cpp
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@ -246,7 +246,7 @@ sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
// appropriate location, we can try to sink the current instruction // appropriate location, we can try to sink the current instruction
// past it. // past it.
if (!KillMI || KillMI->getParent() != MBB || KillMI == MI || if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
KillMI == OldPos || KillMI->isTerminator()) MachineBasicBlock::iterator(KillMI) == OldPos || KillMI->isTerminator())
return false; return false;
// If any of the definitions are used by another instruction between the // If any of the definitions are used by another instruction between the
@ -260,16 +260,15 @@ sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
++KillPos; ++KillPos;
unsigned NumVisited = 0; unsigned NumVisited = 0;
for (MachineBasicBlock::iterator I = std::next(OldPos); I != KillPos; ++I) { for (MachineInstr &OtherMI : llvm::make_range(std::next(OldPos), KillPos)) {
MachineInstr *OtherMI = I;
// DBG_VALUE cannot be counted against the limit. // DBG_VALUE cannot be counted against the limit.
if (OtherMI->isDebugValue()) if (OtherMI.isDebugValue())
continue; continue;
if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost. if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
return false; return false;
++NumVisited; ++NumVisited;
for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = OtherMI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = OtherMI->getOperand(i); MachineOperand &MO = OtherMI.getOperand(i);
if (!MO.isReg()) if (!MO.isReg())
continue; continue;
unsigned MOReg = MO.getReg(); unsigned MOReg = MO.getReg();
@ -278,8 +277,8 @@ sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
if (DefReg == MOReg) if (DefReg == MOReg)
return false; return false;
if (MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))) { if (MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))) {
if (OtherMI == KillMI && MOReg == SavedReg) if (&OtherMI == KillMI && MOReg == SavedReg)
// Save the operand that kills the register. We want to unset the kill // Save the operand that kills the register. We want to unset the kill
// marker if we can sink MI past it. // marker if we can sink MI past it.
KillMO = &MO; KillMO = &MO;
@ -898,19 +897,18 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
unsigned NumVisited = 0; unsigned NumVisited = 0;
MachineBasicBlock::iterator KillPos = KillMI; MachineBasicBlock::iterator KillPos = KillMI;
++KillPos; ++KillPos;
for (MachineBasicBlock::iterator I = End; I != KillPos; ++I) { for (MachineInstr &OtherMI : llvm::make_range(End, KillPos)) {
MachineInstr *OtherMI = I;
// DBG_VALUE cannot be counted against the limit. // DBG_VALUE cannot be counted against the limit.
if (OtherMI->isDebugValue()) if (OtherMI.isDebugValue())
continue; continue;
if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost. if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
return false; return false;
++NumVisited; ++NumVisited;
if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() || if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
OtherMI->isBranch() || OtherMI->isTerminator()) OtherMI.isBranch() || OtherMI.isTerminator())
// Don't move pass calls, etc. // Don't move pass calls, etc.
return false; return false;
for (const MachineOperand &MO : OtherMI->operands()) { for (const MachineOperand &MO : OtherMI.operands()) {
if (!MO.isReg()) if (!MO.isReg())
continue; continue;
unsigned MOReg = MO.getReg(); unsigned MOReg = MO.getReg();
@ -928,8 +926,8 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
} else { } else {
if (Defs.count(MOReg)) if (Defs.count(MOReg))
return false; return false;
bool isKill = MO.isKill() || bool isKill =
(LIS && isPlainlyKilled(OtherMI, MOReg, LIS)); MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS));
if (MOReg != Reg && if (MOReg != Reg &&
((isKill && Uses.count(MOReg)) || Kills.count(MOReg))) ((isKill && Uses.count(MOReg)) || Kills.count(MOReg)))
// Don't want to extend other live ranges and update kills. // Don't want to extend other live ranges and update kills.
@ -938,7 +936,7 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
// We can't schedule across a use of the register in question. // We can't schedule across a use of the register in question.
return false; return false;
// Ensure that if this is register in question, its the kill we expect. // Ensure that if this is register in question, its the kill we expect.
assert((MOReg != Reg || OtherMI == KillMI) && assert((MOReg != Reg || &OtherMI == KillMI) &&
"Found multiple kills of a register in a basic block"); "Found multiple kills of a register in a basic block");
} }
} }
@ -954,8 +952,7 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
// We have to move the copies first so that the MBB is still well-formed // We have to move the copies first so that the MBB is still well-formed
// when calling handleMove(). // when calling handleMove().
for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) { for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) {
MachineInstr *CopyMI = MBBI; auto CopyMI = MBBI++;
++MBBI;
MBB->splice(InsertPos, MBB, CopyMI); MBB->splice(InsertPos, MBB, CopyMI);
LIS->handleMove(*CopyMI); LIS->handleMove(*CopyMI);
InsertPos = CopyMI; InsertPos = CopyMI;
@ -1073,21 +1070,20 @@ rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
// Check if the reschedule will not break depedencies. // Check if the reschedule will not break depedencies.
unsigned NumVisited = 0; unsigned NumVisited = 0;
MachineBasicBlock::iterator KillPos = KillMI; for (MachineInstr &OtherMI :
for (MachineBasicBlock::iterator I = mi; I != KillPos; ++I) { llvm::make_range(mi, MachineBasicBlock::iterator(KillMI))) {
MachineInstr *OtherMI = I;
// DBG_VALUE cannot be counted against the limit. // DBG_VALUE cannot be counted against the limit.
if (OtherMI->isDebugValue()) if (OtherMI.isDebugValue())
continue; continue;
if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost. if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
return false; return false;
++NumVisited; ++NumVisited;
if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() || if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
OtherMI->isBranch() || OtherMI->isTerminator()) OtherMI.isBranch() || OtherMI.isTerminator())
// Don't move pass calls, etc. // Don't move pass calls, etc.
return false; return false;
SmallVector<unsigned, 2> OtherDefs; SmallVector<unsigned, 2> OtherDefs;
for (const MachineOperand &MO : OtherMI->operands()) { for (const MachineOperand &MO : OtherMI.operands()) {
if (!MO.isReg()) if (!MO.isReg())
continue; continue;
unsigned MOReg = MO.getReg(); unsigned MOReg = MO.getReg();
@ -1101,8 +1097,8 @@ rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
if (Kills.count(MOReg)) if (Kills.count(MOReg))
// Don't want to extend other live ranges and update kills. // Don't want to extend other live ranges and update kills.
return false; return false;
if (OtherMI != MI && MOReg == Reg && if (&OtherMI != MI && MOReg == Reg &&
!(MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS)))) !(MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))))
// We can't schedule across a use of the register in question. // We can't schedule across a use of the register in question.
return false; return false;
} else { } else {
@ -1517,7 +1513,7 @@ TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
// Update DistanceMap. // Update DistanceMap.
MachineBasicBlock::iterator PrevMI = MI; MachineBasicBlock::iterator PrevMI = MI;
--PrevMI; --PrevMI;
DistanceMap.insert(std::make_pair(PrevMI, Dist)); DistanceMap.insert(std::make_pair(&*PrevMI, Dist));
DistanceMap[MI] = ++Dist; DistanceMap[MI] = ++Dist;
if (LIS) { if (LIS) {
@ -1649,13 +1645,13 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
if (mi->isRegSequence()) if (mi->isRegSequence())
eliminateRegSequence(mi); eliminateRegSequence(mi);
DistanceMap.insert(std::make_pair(mi, ++Dist)); DistanceMap.insert(std::make_pair(&*mi, ++Dist));
processCopy(&*mi); processCopy(&*mi);
// First scan through all the tied register uses in this instruction // First scan through all the tied register uses in this instruction
// and record a list of pairs of tied operands for each register. // and record a list of pairs of tied operands for each register.
if (!collectTiedOperands(mi, TiedOperands)) { if (!collectTiedOperands(&*mi, TiedOperands)) {
mi = nmi; mi = nmi;
continue; continue;
} }
@ -1688,7 +1684,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
// Now iterate over the information collected above. // Now iterate over the information collected above.
for (auto &TO : TiedOperands) { for (auto &TO : TiedOperands) {
processTiedPairs(mi, TO.second, Dist); processTiedPairs(&*mi, TO.second, Dist);
DEBUG(dbgs() << "\t\trewrite to:\t" << *mi); DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
} }
@ -1732,27 +1728,27 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
/// ///
void TwoAddressInstructionPass:: void TwoAddressInstructionPass::
eliminateRegSequence(MachineBasicBlock::iterator &MBBI) { eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
MachineInstr *MI = MBBI; MachineInstr &MI = *MBBI;
unsigned DstReg = MI->getOperand(0).getReg(); unsigned DstReg = MI.getOperand(0).getReg();
if (MI->getOperand(0).getSubReg() || if (MI.getOperand(0).getSubReg() ||
TargetRegisterInfo::isPhysicalRegister(DstReg) || TargetRegisterInfo::isPhysicalRegister(DstReg) ||
!(MI->getNumOperands() & 1)) { !(MI.getNumOperands() & 1)) {
DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI); DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << MI);
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
SmallVector<unsigned, 4> OrigRegs; SmallVector<unsigned, 4> OrigRegs;
if (LIS) { if (LIS) {
OrigRegs.push_back(MI->getOperand(0).getReg()); OrigRegs.push_back(MI.getOperand(0).getReg());
for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2)
OrigRegs.push_back(MI->getOperand(i).getReg()); OrigRegs.push_back(MI.getOperand(i).getReg());
} }
bool DefEmitted = false; bool DefEmitted = false;
for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) { for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2) {
MachineOperand &UseMO = MI->getOperand(i); MachineOperand &UseMO = MI.getOperand(i);
unsigned SrcReg = UseMO.getReg(); unsigned SrcReg = UseMO.getReg();
unsigned SubIdx = MI->getOperand(i+1).getImm(); unsigned SubIdx = MI.getOperand(i+1).getImm();
// Nothing needs to be inserted for <undef> operands. // Nothing needs to be inserted for <undef> operands.
if (UseMO.isUndef()) if (UseMO.isUndef())
continue; continue;
@ -1762,18 +1758,18 @@ eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
bool isKill = UseMO.isKill(); bool isKill = UseMO.isKill();
if (isKill) if (isKill)
for (unsigned j = i + 2; j < e; j += 2) for (unsigned j = i + 2; j < e; j += 2)
if (MI->getOperand(j).getReg() == SrcReg) { if (MI.getOperand(j).getReg() == SrcReg) {
MI->getOperand(j).setIsKill(); MI.getOperand(j).setIsKill();
UseMO.setIsKill(false); UseMO.setIsKill(false);
isKill = false; isKill = false;
break; break;
} }
// Insert the sub-register copy. // Insert the sub-register copy.
MachineInstr *CopyMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), MachineInstr *CopyMI = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
TII->get(TargetOpcode::COPY)) TII->get(TargetOpcode::COPY))
.addReg(DstReg, RegState::Define, SubIdx) .addReg(DstReg, RegState::Define, SubIdx)
.addOperand(UseMO); .addOperand(UseMO);
// The first def needs an <undef> flag because there is no live register // The first def needs an <undef> flag because there is no live register
// before it. // before it.
@ -1786,7 +1782,7 @@ eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
// Update LiveVariables' kill info. // Update LiveVariables' kill info.
if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg)) if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg))
LV->replaceKillInstruction(SrcReg, *MI, *CopyMI); LV->replaceKillInstruction(SrcReg, MI, *CopyMI);
DEBUG(dbgs() << "Inserted: " << *CopyMI); DEBUG(dbgs() << "Inserted: " << *CopyMI);
} }
@ -1795,13 +1791,13 @@ eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
std::next(MachineBasicBlock::iterator(MI)); std::next(MachineBasicBlock::iterator(MI));
if (!DefEmitted) { if (!DefEmitted) {
DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF"); DEBUG(dbgs() << "Turned: " << MI << " into an IMPLICIT_DEF");
MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); MI.setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j) for (int j = MI.getNumOperands() - 1, ee = 0; j > ee; --j)
MI->RemoveOperand(j); MI.RemoveOperand(j);
} else { } else {
DEBUG(dbgs() << "Eliminated: " << *MI); DEBUG(dbgs() << "Eliminated: " << MI);
MI->eraseFromParent(); MI.eraseFromParent();
} }
// Udpate LiveIntervals. // Udpate LiveIntervals.