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[TII] Allow getMemOpBaseRegImmOfs() to accept negative offsets. NFC.

Browse Source 
http://reviews.llvm.org/D17967

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263021 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2016-03-09 16:00:35 +00:00
parent 9925f81075
commit cd3a68c781
12 changed files with 23 additions and 22 deletions
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2
include/llvm/Target/TargetInstrInfo.h
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@ -973,7 +973,7 @@ public:
/// Get the base register and byte offset of an instruction that reads/writes
/// memory.
virtual bool getMemOpBaseRegImmOfs(MachineInstr *MemOp, unsigned &BaseReg,
unsigned &Offset,
int64_t &Offset,
const TargetRegisterInfo *TRI) const {
return false;
}

10
lib/CodeGen/ImplicitNullChecks.cpp
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@ -46,10 +46,9 @@
using namespace llvm;
static cl::opt<unsigned> PageSize("imp-null-check-page-size",
cl::desc("The page size of the target in "
"bytes"),
cl::init(4096));
static cl::opt<int> PageSize("imp-null-check-page-size",
cl::desc("The page size of the target in bytes"),
cl::init(4096));
#define DEBUG_TYPE "implicit-null-checks"
@ -324,7 +323,8 @@ bool ImplicitNullChecks::analyzeBlockForNullChecks(
for (auto MII = NotNullSucc->begin(), MIE = NotNullSucc->end(); MII != MIE;
++MII) {
MachineInstr *MI = &*MII;
unsigned BaseReg, Offset;
unsigned BaseReg;
int64_t Offset;
if (TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI))
if (MI->mayLoad() && !MI->isPredicable() && BaseReg == PointerReg &&
Offset < PageSize && MI->getDesc().getNumDefs() <= 1 &&

4
lib/CodeGen/MachineScheduler.cpp
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@ -1361,7 +1361,7 @@ class LoadClusterMutation : public ScheduleDAGMutation {
struct LoadInfo {
SUnit *SU;
unsigned BaseReg;
unsigned Offset;
int64_t Offset;
LoadInfo(SUnit *su, unsigned reg, unsigned ofs)
: SU(su), BaseReg(reg), Offset(ofs) {}
@ -1389,7 +1389,7 @@ void LoadClusterMutation::clusterNeighboringLoads(ArrayRef<SUnit*> Loads,
for (unsigned Idx = 0, End = Loads.size(); Idx != End; ++Idx) {
SUnit *SU = Loads[Idx];
unsigned BaseReg;
unsigned Offset;
int64_t Offset;
if (TII->getMemOpBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
LoadRecords.push_back(LoadInfo(SU, BaseReg, Offset));
}

3
lib/CodeGen/MachineSink.cpp
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@ -702,7 +702,8 @@ static bool SinkingPreventsImplicitNullCheck(MachineInstr *MI,
!PredBB->getTerminator()->getMetadata(LLVMContext::MD_make_implicit))
return false;
unsigned BaseReg, Offset;
unsigned BaseReg;
int64_t Offset;
if (!TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI))
return false;

7
lib/Target/AArch64/AArch64InstrInfo.cpp
View File

@ -1313,10 +1313,9 @@ void AArch64InstrInfo::suppressLdStPair(MachineInstr *MI) const {
->setFlags(MOSuppressPair << MachineMemOperand::MOTargetStartBit);
}
bool
AArch64InstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
unsigned &Offset,
const TargetRegisterInfo *TRI) const {
bool AArch64InstrInfo::getMemOpBaseRegImmOfs(
MachineInstr *LdSt, unsigned &BaseReg, int64_t &Offset,
const TargetRegisterInfo *TRI) const {
switch (LdSt->getOpcode()) {
default:
return false;

2
lib/Target/AArch64/AArch64InstrInfo.h
View File

@ -91,7 +91,7 @@ public:
void suppressLdStPair(MachineInstr *MI) const;
bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
unsigned &Offset,
int64_t &Offset,
const TargetRegisterInfo *TRI) const override;
bool getMemOpBaseRegImmOfsWidth(MachineInstr *LdSt, unsigned &BaseReg,

2
lib/Target/AArch64/AArch64StorePairSuppress.cpp
View File

@ -141,7 +141,7 @@ bool AArch64StorePairSuppress::runOnMachineFunction(MachineFunction &MF) {
if (!isNarrowFPStore(MI))
continue;
unsigned BaseReg;
unsigned Offset;
int64_t Offset;
if (TII->getMemOpBaseRegImmOfs(&MI, BaseReg, Offset, TRI)) {
if (PrevBaseReg == BaseReg) {
// If this block can take STPs, skip ahead to the next block.

6
lib/Target/AMDGPU/SIInstrInfo.cpp
View File

@ -202,7 +202,7 @@ static bool isStride64(unsigned Opc) {
}
bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
unsigned &Offset,
int64_t &Offset,
const TargetRegisterInfo *TRI) const {
unsigned Opc = LdSt->getOpcode();
@ -1160,8 +1160,8 @@ static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
MachineInstr *MIb) const {
unsigned BaseReg0, Offset0;
unsigned BaseReg1, Offset1;
unsigned BaseReg0, BaseReg1;
int64_t Offset0, Offset1;
if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) &&
getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) {

2
lib/Target/AMDGPU/SIInstrInfo.h
View File

@ -91,7 +91,7 @@ public:
int64_t &Offset2) const override;
bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
unsigned &Offset,
int64_t &Offset,
const TargetRegisterInfo *TRI) const final;
bool shouldClusterLoads(MachineInstr *FirstLdSt,

3
lib/Target/AMDGPU/SIMachineScheduler.cpp
View File

@ -1879,7 +1879,8 @@ void SIScheduleDAGMI::schedule()
for (unsigned i = 0, e = (unsigned)SUnits.size(); i != e; ++i) {
SUnit *SU = &SUnits[i];
unsigned BaseLatReg, OffLatReg;
unsigned BaseLatReg;
int64_t OffLatReg;
if (SITII->isLowLatencyInstruction(SU->getInstr())) {
IsLowLatencySU[i] = 1;
if (SITII->getMemOpBaseRegImmOfs(SU->getInstr(), BaseLatReg,

2
lib/Target/X86/X86InstrInfo.cpp
View File

@ -4612,7 +4612,7 @@ static unsigned getLoadStoreRegOpcode(unsigned Reg,
}
bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr *MemOp, unsigned &BaseReg,
unsigned &Offset,
int64_t &Offset,
const TargetRegisterInfo *TRI) const {
const MCInstrDesc &Desc = MemOp->getDesc();
int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags, MemOp->getOpcode());

2
lib/Target/X86/X86InstrInfo.h
View File

@ -312,7 +312,7 @@ public:
bool AllowModify) const override;
bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
unsigned &Offset,
int64_t &Offset,
const TargetRegisterInfo *TRI) const override;
bool AnalyzeBranchPredicate(MachineBasicBlock &MBB,
TargetInstrInfo::MachineBranchPredicate &MBP,