Add dummy inline asm handling for 'r' constraint. This fixes PR4778

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80085 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/MSP430/AsmPrinter/MSP430AsmPrinter.cpp

@@ -58,6 +58,9 @@ namespace {
     void printCCOperand(const MachineInstr *MI, int OpNum);
     void printInstruction(const MachineInstr *MI);  // autogenerated.
     void printMachineInstruction(const MachineInstr * MI);
+    bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
+                         unsigned AsmVariant,
+                         const char *ExtraCode);
 
     void emitFunctionHeader(const MachineFunction &MF);
     bool runOnMachineFunction(MachineFunction &F);
@@ -243,6 +246,19 @@ void MSP430AsmPrinter::printCCOperand(const MachineInstr *MI, int OpNum) {
   }
 }
 
+/// PrintAsmOperand - Print out an operand for an inline asm expression.
+///
+bool MSP430AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
+                                       unsigned AsmVariant,
+                                       const char *ExtraCode) {
+  // Does this asm operand have a single letter operand modifier?
+  if (ExtraCode && ExtraCode[0])
+    return true; // Unknown modifier.
+
+  printOperand(MI, OpNo);
+  return false;
+}
+
 // Force static initialization.
 extern "C" void LLVMInitializeMSP430AsmPrinter() {
   RegisterAsmPrinter<MSP430AsmPrinter> X(TheMSP430Target);

lib/Target/MSP430/MSP430ISelLowering.cpp

@@ -150,6 +150,44 @@ unsigned MSP430TargetLowering::getFunctionAlignment(const Function *F) const {
   return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 4;
 }
 
+//===----------------------------------------------------------------------===//
+//                       MSP430 Inline Assembly Support
+//===----------------------------------------------------------------------===//
+
+/// getConstraintType - Given a constraint letter, return the type of
+/// constraint it is for this target.
+TargetLowering::ConstraintType
+MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
+  if (Constraint.size() == 1) {
+    switch (Constraint[0]) {
+    case 'r':
+      return C_RegisterClass;
+    default:
+      break;
+    }
+  }
+  return TargetLowering::getConstraintType(Constraint);
+}
+
+std::pair<unsigned, const TargetRegisterClass*>
+MSP430TargetLowering::
+getRegForInlineAsmConstraint(const std::string &Constraint,
+                             EVT VT) const {
+  if (Constraint.size() == 1) {
+    // GCC Constraint Letters
+    switch (Constraint[0]) {
+    default: break;
+    case 'r':   // GENERAL_REGS
+      if (VT == MVT::i8)
+        return std::make_pair(0U, MSP430::GR8RegisterClass);
+
+      return std::make_pair(0U, MSP430::GR16RegisterClass);
+    }
+  }
+
+  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
+}
+
 //===----------------------------------------------------------------------===//
 //                      Calling Convention Implementation
 //===----------------------------------------------------------------------===//

lib/Target/MSP430/MSP430ISelLowering.h

@@ -84,6 +84,11 @@ namespace llvm {
     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
     SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG);
 
+    TargetLowering::ConstraintType
+    getConstraintType(const std::string &Constraint) const;
+    std::pair<unsigned, const TargetRegisterClass*>
+    getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
+
     MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI,
                                                    MachineBasicBlock *BB) const;
 

test/CodeGen/MSP430/inline-asm.ll

@@ -0,0 +1,16 @@
+; RUN: llvm-as < %s | llc
+; PR4778
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+
+define signext i8 @__nesc_atomic_start() nounwind {
+entry:
+  %0 = tail call i16 asm sideeffect "mov    r2, $0", "=r"() nounwind ; <i16> [#uses=1]
+  %1 = trunc i16 %0 to i8                         ; <i8> [#uses=1]
+  %and3 = lshr i8 %1, 3                           ; <i8> [#uses=1]
+  %conv1 = and i8 %and3, 1                        ; <i8> [#uses=1]
+  tail call void asm sideeffect "dint", ""() nounwind
+  tail call void asm sideeffect "nop", ""() nounwind
+  tail call void asm sideeffect "", "~{memory}"() nounwind
+  ret i8 %conv1
+}