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Unify the logic in SelectAtomicLoadAdd and SelectAtomicLoadArith
- Merge the processing of LOAD_ADD with other atomic load-arith operations - Separate the logic getting target constant for atomic-load-op and add an optimization for atomic-load-add on i16 with negative value - Optimize a minor case for atomic-fetch-add i16 with negative operand. Test case is revised. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164243 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michael Liao
parent
fc879791f2
commit
cd9ede9fc0
@ -191,7 +191,6 @@ namespace {
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SDNode *Select(SDNode *N);
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SDNode *SelectGather(SDNode *N, unsigned Opc);
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SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
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SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT);
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SDNode *SelectAtomicLoadArith(SDNode *Node, EVT NVT);
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bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
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@ -1480,6 +1479,7 @@ SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
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SDValue In1 = Node->getOperand(1);
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SDValue In2L = Node->getOperand(2);
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SDValue In2H = Node->getOperand(3);
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SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
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if (!SelectAddr(Node, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
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return NULL;
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@ -1493,159 +1493,13 @@ SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
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return ResNode;
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}
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// FIXME: Figure out some way to unify this with the 'or' and other code
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// below.
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SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
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if (Node->hasAnyUseOfValue(0))
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return 0;
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// Optimize common patterns for __sync_add_and_fetch and
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// __sync_sub_and_fetch where the result is not used. This allows us
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// to use "lock" version of add, sub, inc, dec instructions.
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// FIXME: Do not use special instructions but instead add the "lock"
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// prefix to the target node somehow. The extra information will then be
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// transferred to machine instruction and it denotes the prefix.
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SDValue Chain = Node->getOperand(0);
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SDValue Ptr = Node->getOperand(1);
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SDValue Val = Node->getOperand(2);
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SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
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if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
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return 0;
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bool isInc = false, isDec = false, isSub = false, isCN = false;
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val);
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if (CN && CN->getSExtValue() == (int32_t)CN->getSExtValue()) {
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isCN = true;
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int64_t CNVal = CN->getSExtValue();
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if (CNVal == 1)
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isInc = true;
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else if (CNVal == -1)
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isDec = true;
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else if (CNVal >= 0)
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Val = CurDAG->getTargetConstant(CNVal, NVT);
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else {
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isSub = true;
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Val = CurDAG->getTargetConstant(-CNVal, NVT);
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}
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} else if (Val.hasOneUse() &&
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Val.getOpcode() == ISD::SUB &&
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X86::isZeroNode(Val.getOperand(0))) {
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isSub = true;
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Val = Val.getOperand(1);
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}
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DebugLoc dl = Node->getDebugLoc();
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unsigned Opc = 0;
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switch (NVT.getSimpleVT().SimpleTy) {
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default: return 0;
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case MVT::i8:
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if (isInc)
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Opc = X86::LOCK_INC8m;
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else if (isDec)
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Opc = X86::LOCK_DEC8m;
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else if (isSub) {
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if (isCN)
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Opc = X86::LOCK_SUB8mi;
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else
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Opc = X86::LOCK_SUB8mr;
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} else {
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if (isCN)
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Opc = X86::LOCK_ADD8mi;
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else
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Opc = X86::LOCK_ADD8mr;
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}
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break;
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case MVT::i16:
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if (isInc)
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Opc = X86::LOCK_INC16m;
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else if (isDec)
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Opc = X86::LOCK_DEC16m;
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else if (isSub) {
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if (isCN) {
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if (immSext8(Val.getNode()))
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Opc = X86::LOCK_SUB16mi8;
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else
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Opc = X86::LOCK_SUB16mi;
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} else
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Opc = X86::LOCK_SUB16mr;
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} else {
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if (isCN) {
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if (immSext8(Val.getNode()))
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Opc = X86::LOCK_ADD16mi8;
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else
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Opc = X86::LOCK_ADD16mi;
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} else
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Opc = X86::LOCK_ADD16mr;
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}
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break;
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case MVT::i32:
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if (isInc)
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Opc = X86::LOCK_INC32m;
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else if (isDec)
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Opc = X86::LOCK_DEC32m;
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else if (isSub) {
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if (isCN) {
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if (immSext8(Val.getNode()))
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Opc = X86::LOCK_SUB32mi8;
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else
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Opc = X86::LOCK_SUB32mi;
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} else
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Opc = X86::LOCK_SUB32mr;
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} else {
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if (isCN) {
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if (immSext8(Val.getNode()))
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Opc = X86::LOCK_ADD32mi8;
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else
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Opc = X86::LOCK_ADD32mi;
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} else
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Opc = X86::LOCK_ADD32mr;
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}
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break;
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case MVT::i64:
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if (isInc)
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Opc = X86::LOCK_INC64m;
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else if (isDec)
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Opc = X86::LOCK_DEC64m;
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else if (isSub) {
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Opc = X86::LOCK_SUB64mr;
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if (isCN) {
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if (immSext8(Val.getNode()))
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Opc = X86::LOCK_SUB64mi8;
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else if (i64immSExt32(Val.getNode()))
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Opc = X86::LOCK_SUB64mi32;
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}
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} else {
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Opc = X86::LOCK_ADD64mr;
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if (isCN) {
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if (immSext8(Val.getNode()))
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Opc = X86::LOCK_ADD64mi8;
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else if (i64immSExt32(Val.getNode()))
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Opc = X86::LOCK_ADD64mi32;
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}
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}
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break;
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}
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SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
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dl, NVT), 0);
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
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if (isInc || isDec) {
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SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
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SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6), 0);
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cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
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SDValue RetVals[] = { Undef, Ret };
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return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
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} else {
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SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
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SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0);
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cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
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SDValue RetVals[] = { Undef, Ret };
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return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
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}
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}
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/// Atomic opcode table
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///
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enum AtomicOpc {
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ADD,
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SUB,
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INC,
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DEC,
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OR,
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AND,
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XOR,
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@ -1668,6 +1522,58 @@ enum AtomicSz {
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};
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static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
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{
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X86::LOCK_ADD8mi,
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X86::LOCK_ADD8mr,
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X86::LOCK_ADD16mi8,
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X86::LOCK_ADD16mi,
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X86::LOCK_ADD16mr,
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X86::LOCK_ADD32mi8,
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X86::LOCK_ADD32mi,
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X86::LOCK_ADD32mr,
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X86::LOCK_ADD64mi8,
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X86::LOCK_ADD64mi32,
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X86::LOCK_ADD64mr,
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},
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{
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X86::LOCK_SUB8mi,
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X86::LOCK_SUB8mr,
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X86::LOCK_SUB16mi8,
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X86::LOCK_SUB16mi,
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X86::LOCK_SUB16mr,
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X86::LOCK_SUB32mi8,
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X86::LOCK_SUB32mi,
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X86::LOCK_SUB32mr,
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X86::LOCK_SUB64mi8,
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X86::LOCK_SUB64mi32,
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X86::LOCK_SUB64mr,
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},
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{
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0,
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X86::LOCK_INC8m,
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0,
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0,
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X86::LOCK_INC16m,
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0,
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0,
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X86::LOCK_INC32m,
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0,
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0,
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X86::LOCK_INC64m,
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},
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{
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0,
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X86::LOCK_DEC8m,
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0,
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0,
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X86::LOCK_DEC16m,
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0,
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0,
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X86::LOCK_DEC32m,
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0,
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0,
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X86::LOCK_DEC64m,
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},
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{
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X86::LOCK_OR8mi,
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X86::LOCK_OR8mr,
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@ -1679,7 +1585,7 @@ static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
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X86::LOCK_OR32mr,
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X86::LOCK_OR64mi8,
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X86::LOCK_OR64mi32,
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X86::LOCK_OR64mr
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X86::LOCK_OR64mr,
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},
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{
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X86::LOCK_AND8mi,
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@ -1692,7 +1598,7 @@ static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
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X86::LOCK_AND32mr,
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X86::LOCK_AND64mi8,
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X86::LOCK_AND64mi32,
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X86::LOCK_AND64mr
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X86::LOCK_AND64mr,
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},
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{
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X86::LOCK_XOR8mi,
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@ -1705,18 +1611,74 @@ static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
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X86::LOCK_XOR32mr,
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X86::LOCK_XOR64mi8,
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X86::LOCK_XOR64mi32,
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X86::LOCK_XOR64mr
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X86::LOCK_XOR64mr,
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}
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};
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// Return the target constant operand for atomic-load-op and do simple
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// translations, such as from atomic-load-add to lock-sub. The return value is
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// one of the following 3 cases:
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// + target-constant, the operand could be supported as a target constant.
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// + empty, the operand is not needed any more with the new op selected.
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// + non-empty, otherwise.
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static SDValue getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG,
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DebugLoc dl,
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enum AtomicOpc &Op, EVT NVT,
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SDValue Val) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val)) {
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int64_t CNVal = CN->getSExtValue();
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// Quit if not 32-bit imm.
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if ((int32_t)CNVal != CNVal)
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return Val;
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// For atomic-load-add, we could do some optimizations.
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if (Op == ADD) {
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// Translate to INC/DEC if ADD by 1 or -1.
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if ((CNVal == 1) || (CNVal == -1)) {
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Op = (CNVal == 1) ? INC : DEC;
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// No more constant operand after being translated into INC/DEC.
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return SDValue();
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}
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// Translate to SUB if ADD by negative value.
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if (CNVal < 0) {
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Op = SUB;
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CNVal = -CNVal;
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}
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}
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return CurDAG->getTargetConstant(CNVal, NVT);
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}
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// If the value operand is single-used, try to optimize it.
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if (Op == ADD && Val.hasOneUse()) {
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// Translate (atomic-load-add ptr (sub 0 x)) back to (lock-sub x).
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if (Val.getOpcode() == ISD::SUB && X86::isZeroNode(Val.getOperand(0))) {
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Op = SUB;
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return Val.getOperand(1);
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}
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// A special case for i16, which needs truncating as, in most cases, it's
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// promoted to i32. We will translate
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// (atomic-load-add (truncate (sub 0 x))) to (lock-sub (EXTRACT_SUBREG x))
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if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 &&
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Val.getOperand(0).getOpcode() == ISD::SUB &&
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X86::isZeroNode(Val.getOperand(0).getOperand(0))) {
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Op = SUB;
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Val = Val.getOperand(0);
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return CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, NVT,
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Val.getOperand(1));
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}
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}
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return Val;
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}
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SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, EVT NVT) {
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if (Node->hasAnyUseOfValue(0))
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return 0;
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DebugLoc dl = Node->getDebugLoc();
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// Optimize common patterns for __sync_or_and_fetch and similar arith
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// operations where the result is not used. This allows us to use the "lock"
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// version of the arithmetic instruction.
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// FIXME: Same as for 'add' and 'sub', try to merge those down here.
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SDValue Chain = Node->getOperand(0);
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SDValue Ptr = Node->getOperand(1);
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SDValue Val = Node->getOperand(2);
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@ -1727,6 +1689,8 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, EVT NVT) {
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// Which index into the table.
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enum AtomicOpc Op;
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switch (Node->getOpcode()) {
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default:
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return 0;
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case ISD::ATOMIC_LOAD_OR:
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Op = OR;
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break;
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@ -1736,16 +1700,14 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, EVT NVT) {
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case ISD::ATOMIC_LOAD_XOR:
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Op = XOR;
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break;
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default:
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return 0;
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}
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bool isCN = false;
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val);
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if (CN && (int32_t)CN->getSExtValue() == CN->getSExtValue()) {
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isCN = true;
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Val = CurDAG->getTargetConstant(CN->getSExtValue(), NVT);
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case ISD::ATOMIC_LOAD_ADD:
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Op = ADD;
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break;
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}
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Val = getAtomicLoadArithTargetConstant(CurDAG, dl, Op, NVT, Val);
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bool isUnOp = !Val.getNode();
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bool isCN = Val.getNode() && (Val.getOpcode() == ISD::TargetConstant);
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unsigned Opc = 0;
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switch (NVT.getSimpleVT().SimpleTy) {
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@ -1787,13 +1749,20 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, EVT NVT) {
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assert(Opc != 0 && "Invalid arith lock transform!");
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DebugLoc dl = Node->getDebugLoc();
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SDValue Ret;
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SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
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dl, NVT), 0);
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
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SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
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SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0);
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if (isUnOp) {
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SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
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Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops,
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array_lengthof(Ops)), 0);
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} else {
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SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
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Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops,
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array_lengthof(Ops)), 0);
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}
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cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
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SDValue RetVals[] = { Undef, Ret };
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return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
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@ -2089,15 +2058,10 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
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break;
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}
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case ISD::ATOMIC_LOAD_ADD: {
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SDNode *RetVal = SelectAtomicLoadAdd(Node, NVT);
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if (RetVal)
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return RetVal;
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break;
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}
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case ISD::ATOMIC_LOAD_XOR:
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case ISD::ATOMIC_LOAD_AND:
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case ISD::ATOMIC_LOAD_OR: {
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case ISD::ATOMIC_LOAD_OR:
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case ISD::ATOMIC_LOAD_ADD: {
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SDNode *RetVal = SelectAtomicLoadArith(Node, NVT);
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if (RetVal)
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return RetVal;
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@ -178,7 +178,8 @@ entry:
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define void @sub2(i16* nocapture %p, i32 %v) nounwind ssp {
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entry:
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; CHECK: sub2:
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; CHECK: negl
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; CHECK-NOT: negl
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; CHECK: subw
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%0 = trunc i32 %v to i16 ; <i16> [#uses=1]
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%1 = atomicrmw sub i16* %p, i16 %0 monotonic
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ret void
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