RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2025-04-03 00:31:49 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[mips] SelectionDAGISel subclasses now follow the optimization level.

Browse Source 
Summary:
It was recently discovered that, for Mips's SelectionDAGISel subclasses,
all optimization levels caused SelectionDAGISel to behave like -O2.

This change adds the necessary plumbing to initialize the optimization level.

Reviewers: andrew.w.kaylor

Subscribers: andrew.w.kaylor, sdardis, dean, llvm-commits, vradosavljevic, petarj, qcolombet, probinson, dsanders

Differential Revision: https://reviews.llvm.org/D14900

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275410 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2016-07-14 13:25:22 +00:00
parent 1ab13082a4
commit ce8041577b
7 changed files with 40 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/Target/Mips/Mips16ISelDAGToDAG.cpp
View File

@ -254,6 +254,7 @@ bool Mips16DAGToDAGISel::trySelect(SDNode *Node) {
return false;
}
FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM) {
return new Mips16DAGToDAGISel(TM);
FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM,
CodeGenOpt::Level OptLevel) {
return new Mips16DAGToDAGISel(TM, OptLevel);
}

6
lib/Target/Mips/Mips16ISelDAGToDAG.h
View File

@ -20,7 +20,8 @@ namespace llvm {
class Mips16DAGToDAGISel : public MipsDAGToDAGISel {
public:
explicit Mips16DAGToDAGISel(MipsTargetMachine &TM) : MipsDAGToDAGISel(TM) {}
explicit Mips16DAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
: MipsDAGToDAGISel(TM, OL) {}
private:
std::pair<SDNode *, SDNode *> selectMULT(SDNode *N, unsigned Opc,
@ -47,7 +48,8 @@ private:
void initMips16SPAliasReg(MachineFunction &MF);
};
FunctionPass *createMips16ISelDag(MipsTargetMachine &TM);
FunctionPass *createMips16ISelDag(MipsTargetMachine &TM,
CodeGenOpt::Level OptLevel);
}
#endif

4
lib/Target/Mips/MipsISelDAGToDAG.h
View File

@ -31,8 +31,8 @@ namespace llvm {
class MipsDAGToDAGISel : public SelectionDAGISel {
public:
explicit MipsDAGToDAGISel(MipsTargetMachine &TM)
: SelectionDAGISel(TM), Subtarget(nullptr) {}
explicit MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
: SelectionDAGISel(TM, OL), Subtarget(nullptr) {}
// Pass Name
const char *getPassName() const override {

5
lib/Target/Mips/MipsSEISelDAGToDAG.cpp
View File

@ -1033,6 +1033,7 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
return true;
}
FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
return new MipsSEDAGToDAGISel(TM);
FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM,
CodeGenOpt::Level OptLevel) {
return new MipsSEDAGToDAGISel(TM, OptLevel);
}

7
lib/Target/Mips/MipsSEISelDAGToDAG.h
View File

@ -21,7 +21,8 @@ namespace llvm {
class MipsSEDAGToDAGISel : public MipsDAGToDAGISel {
public:
explicit MipsSEDAGToDAGISel(MipsTargetMachine &TM) : MipsDAGToDAGISel(TM) {}
explicit MipsSEDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
: MipsDAGToDAGISel(TM, OL) {}
private:
@ -131,8 +132,8 @@ private:
std::vector<SDValue> &OutOps) override;
};
FunctionPass *createMipsSEISelDag(MipsTargetMachine &TM);
FunctionPass *createMipsSEISelDag(MipsTargetMachine &TM,
CodeGenOpt::Level OptLevel);
}
#endif

4
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -229,8 +229,8 @@ void MipsPassConfig::addIRPasses() {
// the ISelDag to gen Mips code.
bool MipsPassConfig::addInstSelector() {
addPass(createMipsModuleISelDagPass(getMipsTargetMachine()));
addPass(createMips16ISelDag(getMipsTargetMachine()));
addPass(createMipsSEISelDag(getMipsTargetMachine()));
addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel()));
addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel()));
return false;
}

22
test/CodeGen/Mips/selectiondag-optlevel.ll Normal file
View File

@ -0,0 +1,22 @@
; RUN: llc -march=mips -fast-isel=false -O0 < %s 2>&1 | FileCheck %s -check-prefix=O0
; RUN: llc -march=mips -fast-isel=false -O2 < %s 2>&1 | FileCheck %s -check-prefix=O2
; At -O0, DAGCombine won't try to merge these consecutive loads but it will at
; -O2.
define void @foo() nounwind {
entry:
%0 = alloca [2 x i8], align 32
%1 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 0
store i8 1, i8* %1
%2 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 1
store i8 1, i8* %2
ret void
}
; O0: addiu $[[REG:[0-9]+]], $zero, 1
; O0-DAG: sb $[[REG]], 0($sp)
; O0-DAG: sb $[[REG]], 1($sp)
; O2: addiu $[[REG:[0-9]+]], $zero, 257
; O2: sh $[[REG]], 0($sp)