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[Hexagon] Adding combine reg, reg with predicated forms.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223667 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2014-12-08 17:33:06 +00:00
parent 83fbd8dcd2
commit cf2daa3671
3 changed files with 13 additions and 0 deletions
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7
lib/Target/Hexagon/HexagonInstrInfo.td
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@ -208,6 +208,13 @@ def: BinOp32_pat<xor, A2_xor, i32>;
let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0,
isCodeGenOnly = 0 in {
def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>;
let isPredicable = 1 in
def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>;
// Conditional combinew uses "newt/f" instead of "t/fnew".
def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
}
let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in

2
test/MC/Disassembler/Hexagon/alu32_perm.txt
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@ -10,6 +10,8 @@
# CHECK: r17 = combine(r31.l, r21.l)
0xb0 0xe2 0x0f 0x7c
# CHECK: r17:16 = combine(#21, #31)
0x10 0xdf 0x15 0xf5
# CHECK: r17:16 = combine(r21, r31)
0xf1 0xc3 0x75 0x73
# CHECK: r17 = mux(p3, r21, #31)
0xb1 0xc2 0xff 0x73

4
test/MC/Disassembler/Hexagon/alu32_pred.txt
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@ -6,6 +6,10 @@
# CHECK: if (p3) r17 = aslh(r21)
0x11 0xe3 0x35 0x70
# CHECK: if (p3) r17 = asrh(r21)
0x70 0xdf 0x15 0xfd
# CHECK: if (p3) r17:16 = combine(r21, r31)
0xf0 0xdf 0x15 0xfd
# CHECK: if (!p3) r17:16 = combine(r21, r31)
0x71 0xdf 0x15 0xf9
# CHECK: if (p3) r17 = and(r21, r31)
0x71 0xdf 0x35 0xf9