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Remember to use the correct register when rematerializing for snippets.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128469 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-03-29 17:47:02 +00:00
parent c1d22d8adb
commit cf610d07de
2 changed files with 7 additions and 6 deletions
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12
lib/CodeGen/InlineSpiller.cpp
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@ -580,7 +580,7 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg,
DEBUG(dbgs() << "\tadding <undef> flags: "); DEBUG(dbgs() << "\tadding <undef> flags: ");
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i); MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && MO.isUse() && MO.getReg() == Edit->getReg()) if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
MO.setIsUndef(); MO.setIsUndef();
} }
DEBUG(dbgs() << UseIdx << '\t' << *MI); DEBUG(dbgs() << UseIdx << '\t' << *MI);
@ -601,11 +601,11 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg,
return false; return false;
} }
// If the instruction also writes Edit->getReg(), it had better not require // If the instruction also writes VirtReg.reg, it had better not require the
// the same register for uses and defs. // same register for uses and defs.
bool Reads, Writes; bool Reads, Writes;
SmallVector<unsigned, 8> Ops; SmallVector<unsigned, 8> Ops;
tie(Reads, Writes) = MI->readsWritesVirtualRegister(Edit->getReg(), &Ops); tie(Reads, Writes) = MI->readsWritesVirtualRegister(VirtReg.reg, &Ops);
if (Writes) { if (Writes) {
for (unsigned i = 0, e = Ops.size(); i != e; ++i) { for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(Ops[i]); MachineOperand &MO = MI->getOperand(Ops[i]);
@ -626,7 +626,7 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg,
} }
// Alocate a new register for the remat. // Alocate a new register for the remat.
LiveInterval &NewLI = Edit->create(LIS, VRM); LiveInterval &NewLI = Edit->createFrom(VirtReg.reg, LIS, VRM);
NewLI.markNotSpillable(); NewLI.markNotSpillable();
// Rematting for a copy: Set allocation hint to be the destination register. // Rematting for a copy: Set allocation hint to be the destination register.
@ -642,7 +642,7 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg,
// Replace operands // Replace operands
for (unsigned i = 0, e = Ops.size(); i != e; ++i) { for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(Ops[i]); MachineOperand &MO = MI->getOperand(Ops[i]);
if (MO.isReg() && MO.isUse() && MO.getReg() == Edit->getReg()) { if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
MO.setReg(NewLI.reg); MO.setReg(NewLI.reg);
MO.setIsKill(); MO.setIsKill();
} }

1
lib/CodeGen/LiveRangeEdit.cpp
View File

@ -11,6 +11,7 @@
// is spilled or split. // is spilled or split.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#define DEBUG_TYPE "regalloc"
#include "LiveRangeEdit.h" #include "LiveRangeEdit.h"
#include "VirtRegMap.h" #include "VirtRegMap.h"
#include "llvm/ADT/SetVector.h" #include "llvm/ADT/SetVector.h"