mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-04 10:04:33 +00:00
[X86] Reduce code for setting operations actions by merging into loops across multiple types/ops. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301879 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim
parent
c16e4224e1
commit
cf6b7526dc
@ -785,30 +785,18 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
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setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
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setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
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setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
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setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
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setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
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setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
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setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
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setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
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setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
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for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
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setOperationAction(ISD::SETCC, VT, Custom);
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setOperationAction(ISD::CTPOP, VT, Custom);
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setOperationAction(ISD::CTTZ, VT, Custom);
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}
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setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
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setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
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setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
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setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
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// Custom lower build_vector, vector_shuffle, and extract_vector_elt.
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for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
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setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
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setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
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setOperationAction(ISD::VSELECT, VT, Custom);
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@ -883,18 +871,12 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
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for (auto VT : { MVT::v8i16, MVT::v16i8 }) {
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setOperationAction(ISD::SRL, VT, Custom);
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setOperationAction(ISD::SHL, VT, Custom);
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setOperationAction(ISD::SRA, VT, Custom);
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}
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// In the customized shift lowering, the legal cases in AVX2 will be
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// recognized.
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for (auto VT : { MVT::v4i32, MVT::v2i64 }) {
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setOperationAction(ISD::SRL, VT, Custom);
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setOperationAction(ISD::SHL, VT, Custom);
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setOperationAction(ISD::SRA, VT, Custom);
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// In the customized shift lowering, the legal v4i32/v2i64 cases
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// in AVX2 will be recognized.
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for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
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setOperationAction(ISD::SRL, VT, Custom);
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setOperationAction(ISD::SHL, VT, Custom);
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setOperationAction(ISD::SRA, VT, Custom);
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}
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}
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@ -936,13 +918,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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// SSE41 brings specific instructions for doing vector sign extend even in
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// cases where we don't have SRA.
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Legal);
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Legal);
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Legal);
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setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, MVT::v2i64, Legal);
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setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, MVT::v4i32, Legal);
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setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, MVT::v8i16, Legal);
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for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Legal);
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setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Legal);
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}
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for (MVT VT : MVT::integer_vector_valuetypes()) {
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
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@ -951,19 +930,14 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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}
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// SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
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setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
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for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
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setLoadExtAction(LoadExtOp, MVT::v8i16, MVT::v8i8, Legal);
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setLoadExtAction(LoadExtOp, MVT::v4i32, MVT::v4i8, Legal);
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setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i8, Legal);
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setLoadExtAction(LoadExtOp, MVT::v4i32, MVT::v4i16, Legal);
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setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i16, Legal);
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setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i32, Legal);
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}
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// i8 vectors are custom because the source register and source
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// source memory operand types are not the same width.
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@ -1027,36 +1001,31 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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for (MVT VT : MVT::fp_vector_valuetypes())
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setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
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for (auto VT : { MVT::v32i8, MVT::v16i16 }) {
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// In the customized shift lowering, the legal v8i32/v4i64 cases
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// in AVX2 will be recognized.
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for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
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setOperationAction(ISD::SRL, VT, Custom);
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setOperationAction(ISD::SHL, VT, Custom);
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setOperationAction(ISD::SRA, VT, Custom);
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}
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setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
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setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
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setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
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setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
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setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
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setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
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setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
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setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
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setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
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setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
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setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
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setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
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setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
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setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
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setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
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setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
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for (auto VT : { MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
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setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
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setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
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setOperationAction(ISD::ANY_EXTEND, VT, Custom);
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}
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setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
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setOperationAction(ISD::BITREVERSE, MVT::v32i8, Custom);
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for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
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setOperationAction(ISD::SETCC, VT, Custom);
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setOperationAction(ISD::CTPOP, VT, Custom);
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setOperationAction(ISD::CTTZ, VT, Custom);
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setOperationAction(ISD::CTLZ, VT, Custom);
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@ -1104,27 +1073,14 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
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// AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
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setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
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}
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// In the customized shift lowering, the legal cases in AVX2 will be
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// recognized.
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for (auto VT : { MVT::v8i32, MVT::v4i64 }) {
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setOperationAction(ISD::SRL, VT, Custom);
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setOperationAction(ISD::SHL, VT, Custom);
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setOperationAction(ISD::SRA, VT, Custom);
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for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
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setLoadExtAction(LoadExtOp, MVT::v16i16, MVT::v16i8, Legal);
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setLoadExtAction(LoadExtOp, MVT::v8i32, MVT::v8i8, Legal);
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setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i8, Legal);
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setLoadExtAction(LoadExtOp, MVT::v8i32, MVT::v8i16, Legal);
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setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i16, Legal);
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setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i32, Legal);
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}
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}
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for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
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@ -1273,19 +1229,12 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::VSELECT, MVT::v8i1, Expand);
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setOperationAction(ISD::VSELECT, MVT::v16i1, Expand);
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if (Subtarget.hasDQI()) {
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setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
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setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
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setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
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setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
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setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
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setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
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setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
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setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
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setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
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setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
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setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
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setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
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for (auto VT : { MVT::v2i64, MVT::v4i64, MVT::v8i64 }) {
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setOperationAction(ISD::SINT_TO_FP, VT, Legal);
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setOperationAction(ISD::UINT_TO_FP, VT, Legal);
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setOperationAction(ISD::FP_TO_SINT, VT, Legal);
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setOperationAction(ISD::FP_TO_UINT, VT, Legal);
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}
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if (Subtarget.hasVLX()) {
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// Fast v2f32 SINT_TO_FP( v2i32 ) custom conversion.
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setOperationAction(ISD::SINT_TO_FP, MVT::v2f32, Custom);
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@ -1335,11 +1284,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
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for (auto VT : { MVT::v16f32, MVT::v8f64 }) {
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setOperationAction(ISD::FFLOOR, VT, Legal);
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setOperationAction(ISD::FCEIL, VT, Legal);
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setOperationAction(ISD::FTRUNC, VT, Legal);
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setOperationAction(ISD::FRINT, VT, Legal);
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setOperationAction(ISD::FNEARBYINT, VT, Legal);
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setOperationAction(ISD::FFLOOR, VT, Legal);
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setOperationAction(ISD::FCEIL, VT, Legal);
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setOperationAction(ISD::FTRUNC, VT, Legal);
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setOperationAction(ISD::FRINT, VT, Legal);
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setOperationAction(ISD::FNEARBYINT, VT, Legal);
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}
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i64, Custom);
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@ -1358,7 +1307,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
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setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
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setOperationAction(ISD::MUL, MVT::v8i64, Custom);
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setOperationAction(ISD::MUL, MVT::v8i64, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
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@ -1373,15 +1322,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
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setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
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setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
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setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
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setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
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setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
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setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
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setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
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setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
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setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
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setOperationAction(ISD::ADD, MVT::v8i1, Custom);
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setOperationAction(ISD::ADD, MVT::v16i1, Custom);
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setOperationAction(ISD::SUB, MVT::v8i1, Custom);
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@ -1392,12 +1332,16 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::MUL, MVT::v16i32, Legal);
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for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
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setOperationAction(ISD::ABS, VT, Legal);
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setOperationAction(ISD::SRL, VT, Custom);
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setOperationAction(ISD::SHL, VT, Custom);
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setOperationAction(ISD::SRA, VT, Custom);
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setOperationAction(ISD::CTPOP, VT, Custom);
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setOperationAction(ISD::CTTZ, VT, Custom);
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setOperationAction(ISD::SMAX, VT, Legal);
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setOperationAction(ISD::UMAX, VT, Legal);
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setOperationAction(ISD::SMIN, VT, Legal);
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setOperationAction(ISD::UMIN, VT, Legal);
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setOperationAction(ISD::ABS, VT, Legal);
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setOperationAction(ISD::SRL, VT, Custom);
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setOperationAction(ISD::SHL, VT, Custom);
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setOperationAction(ISD::SRA, VT, Custom);
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setOperationAction(ISD::CTPOP, VT, Custom);
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setOperationAction(ISD::CTTZ, VT, Custom);
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}
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// Need to promote to 64-bit even though we have 32-bit masked instructions
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@ -1541,15 +1485,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::VSELECT, MVT::v64i1, Expand);
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setOperationAction(ISD::BITREVERSE, MVT::v64i8, Custom);
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setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
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setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
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setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
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setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
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setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
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setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
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setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
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setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v32i16, Custom);
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setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
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@ -1580,6 +1515,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
|
||||
setOperationAction(ISD::MSTORE, VT, Legal);
|
||||
setOperationAction(ISD::CTPOP, VT, Custom);
|
||||
setOperationAction(ISD::CTTZ, VT, Custom);
|
||||
setOperationAction(ISD::SMAX, VT, Legal);
|
||||
setOperationAction(ISD::UMAX, VT, Legal);
|
||||
setOperationAction(ISD::SMIN, VT, Legal);
|
||||
setOperationAction(ISD::UMIN, VT, Legal);
|
||||
|
||||
setOperationPromotedToType(ISD::AND, VT, MVT::v8i64);
|
||||
setOperationPromotedToType(ISD::OR, VT, MVT::v8i64);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user