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Add support for -mstrict-align compiler option for ARM targets.

Browse Source 
rdar://12340498


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167620 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2012-11-09 17:29:38 +00:00
parent b754687fd7
commit d054eda441
3 changed files with 18 additions and 9 deletions
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12
include/llvm/Target/TargetOptions.h
View File

@ -48,10 +48,10 @@ namespace llvm {
UseSoftFloat(false), NoZerosInBSS(false), JITExceptionHandling(false),
JITEmitDebugInfo(false), JITEmitDebugInfoToDisk(false),
GuaranteedTailCallOpt(false), DisableTailCalls(false),
StackAlignmentOverride(0), RealignStack(true), EnableFastISel(false),
PositionIndependentExecutable(false), EnableSegmentedStacks(false),
UseInitArray(false), TrapFuncName(""), FloatABIType(FloatABI::Default),
AllowFPOpFusion(FPOpFusion::Standard)
StackAlignmentOverride(0), RealignStack(true), StrictAlign(false),
EnableFastISel(false), PositionIndependentExecutable(false),
EnableSegmentedStacks(false), UseInitArray(false), TrapFuncName(""),
FloatABIType(FloatABI::Default), AllowFPOpFusion(FPOpFusion::Standard)
{}
/// PrintMachineCode - This flag is enabled when the -print-machineinstrs
@ -155,6 +155,10 @@ namespace llvm {
/// automatically realigned, if needed.
unsigned RealignStack : 1;
/// StrictAlign - This flag indicates that all memory accesses must be
/// aligned. (ARM only)
unsigned StrictAlign : 1;
/// SSPBufferSize - The minimum size of buffers that will receive stack
/// smashing protection when -fstack-protection is used.
unsigned SSPBufferSize;

12
lib/Target/ARM/ARMFastISel.cpp
View File

@ -1028,7 +1028,8 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
RC = &ARM::GPRRegClass;
break;
case MVT::i16:
if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
if (Alignment && Alignment < 2 && (!Subtarget->allowsUnalignedMem() ||
TM.Options.StrictAlign))
return false;
if (isThumb2) {
@ -1043,7 +1044,8 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
RC = &ARM::GPRRegClass;
break;
case MVT::i32:
if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
if (Alignment && Alignment < 4 && (!Subtarget->allowsUnalignedMem() ||
TM.Options.StrictAlign))
return false;
if (isThumb2) {
@ -1152,7 +1154,8 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
}
break;
case MVT::i16:
if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
if (Alignment && Alignment < 2 && (!Subtarget->allowsUnalignedMem() ||
TM.Options.StrictAlign))
return false;
if (isThumb2) {
@ -1166,7 +1169,8 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
}
break;
case MVT::i32:
if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
if (Alignment && Alignment < 4 && (!Subtarget->allowsUnalignedMem() ||
TM.Options.StrictAlign))
return false;
if (isThumb2) {

3
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -9119,7 +9119,8 @@ bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
// The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus
bool AllowsUnaligned = Subtarget->allowsUnalignedMem();
bool AllowsUnaligned = Subtarget->allowsUnalignedMem() &&
!getTargetMachine().Options.StrictAlign;
switch (VT.getSimpleVT().SimpleTy) {
default: