RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2025-01-08 04:52:50 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Should not combine ISD::LOCATIONs until we have scheme to remove from

Browse Source 
MachineDebugInfo tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26216 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Laskey 2006-02-15 19:34:44 +00:00
parent 3fdde110eb
commit d0e58e36a9
2 changed files with 2 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -175,9 +175,6 @@ namespace {
SDOperand visitLOAD(SDNode *N);
SDOperand visitSTORE(SDNode *N);
SDOperand visitLOCATION(SDNode *N);
SDOperand visitDEBUGLOC(SDNode *N);
SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
@ -568,8 +565,6 @@ SDOperand DAGCombiner::visit(SDNode *N) {
case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N);
case ISD::LOAD: return visitLOAD(N);
case ISD::STORE: return visitSTORE(N);
case ISD::LOCATION: return visitLOCATION(N);
case ISD::DEBUG_LOC: return visitDEBUGLOC(N);
}
return SDOperand();
}
@ -2162,35 +2157,6 @@ SDOperand DAGCombiner::visitSTORE(SDNode *N) {
return SDOperand();
}
SDOperand DAGCombiner::visitLOCATION(SDNode *N) {
SDOperand Chain = N->getOperand(0);
// Remove redundant locations (last one holds)
if (Chain.getOpcode() == ISD::LOCATION && Chain.hasOneUse()) {
return DAG.getNode(ISD::LOCATION, MVT::Other, Chain.getOperand(0),
N->getOperand(1),
N->getOperand(2),
N->getOperand(3),
N->getOperand(4));
}
return SDOperand();
}
SDOperand DAGCombiner::visitDEBUGLOC(SDNode *N) {
SDOperand Chain = N->getOperand(0);
// Remove redundant debug locations (last one holds)
if (Chain.getOpcode() == ISD::DEBUG_LOC && Chain.hasOneUse()) {
return DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Chain.getOperand(0),
N->getOperand(1),
N->getOperand(2),
N->getOperand(3));
}
return SDOperand();
}
SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");

4
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -519,8 +519,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
} else {
unsigned Line = dyn_cast<ConstantSDNode>(LineOp)->getValue();
unsigned Col = dyn_cast<ConstantSDNode>(ColOp)->getValue();
unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
Ops.push_back(DAG.getConstant(ID, MVT::i32));
Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops);