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[AMDGPU] Refactor VOPC instruction TD definitions

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Differential Revision: https://reviews.llvm.org/D24546

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281903 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Valery Pykhtin 2016-09-19 14:39:49 +00:00
parent 1494db60ab
commit d1be85dd3c
6 changed files with 1118 additions and 648 deletions
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29
lib/Target/AMDGPU/SIInstrFormats.td
View File

@ -157,14 +157,6 @@ class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
let VALU = 1;
}
class VOPCCommon <dag ins, string asm, list<dag> pattern> :
VOPAnyCommon <(outs), ins, asm, pattern> {
let VOPC = 1;
let Size = 4;
let Defs = [VCC];
}
class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> :
VOPAnyCommon <outs, ins, asm, pattern> {
@ -284,14 +276,6 @@ class VOP3e <bits<9> op> : VOP3a <op> {
let Inst{7-0} = vdst;
}
// Encoding used for VOPC instructions encoded as VOP3
// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
class VOP3ce <bits<9> op> : VOP3a <op> {
bits<8> sdst;
let Inst{7-0} = sdst;
}
class VOP3be <bits<9> op> : Enc64 {
bits<8> vdst;
bits<2> src0_modifiers;
@ -316,16 +300,6 @@ class VOP3be <bits<9> op> : Enc64 {
let Inst{63} = src2_modifiers{0};
}
class VOPCe <bits<8> op> : Enc32 {
bits<9> src0;
bits<8> src1;
let Inst{8-0} = src0;
let Inst{16-9} = src1;
let Inst{24-17} = op;
let Inst{31-25} = 0x3e;
}
class VINTRPe <bits<2> op> : Enc32 {
bits<8> vdst;
bits<8> vsrc;
@ -406,9 +380,6 @@ class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
let isCodeGenOnly = 0;
}
class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
VOPCCommon <ins, asm, pattern>, VOPCe <op>;
class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins, asm, pattern> {
let mayLoad = 1;

318
lib/Target/AMDGPU/SIInstrInfo.td
View File

@ -19,14 +19,6 @@ class vop {
field bits<10> VI3;
}
class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
field bits<8> SI = si;
field bits<8> VI = vi;
field bits<9> SI3 = {0, si{7-0}};
field bits<10> VI3 = {0, 0, vi{7-0}};
}
class vop1 <bits<8> si, bits<8> vi = si> : vop {
field bits<8> SI = si;
field bits<8> VI = vi;
@ -654,6 +646,14 @@ class hasModifiers<ValueType SrcVT> {
0));
}
class hasIntModifiers<ValueType SrcVT> {
bit ret =
!if(!eq(SrcVT.Value, i32.Value), 1,
!if(!eq(SrcVT.Value, i64.Value), 1,
0));
}
// Return type of input modifiers operand for specified input operand
class getSrcMod <ValueType VT> {
bit isFP = !if(!eq(VT.Value, f16.Value), 1,
@ -919,7 +919,21 @@ class VOPProfile <list<ValueType> _ArgVT> {
field bit HasDst = !if(!eq(DstVT.Value, untyped.Value), 0, 1);
field bit HasDst32 = HasDst;
field int NumSrcArgs = getNumSrcArgs<Src0VT, Src1VT, Src2VT>.ret;
field bit HasModifiers = hasModifiers<Src0VT>.ret;
field bit HasSrc0 = !if(!eq(Src0VT.Value, untyped.Value), 0, 1);
field bit HasSrc1 = !if(!eq(Src1VT.Value, untyped.Value), 0, 1);
field bit HasSrc2 = !if(!eq(Src2VT.Value, untyped.Value), 0, 1);
field bit HasSrc0Mods = hasModifiers<Src0VT>.ret;
field bit HasSrc1Mods = hasModifiers<Src1VT>.ret;
field bit HasSrc2Mods = hasModifiers<Src2VT>.ret;
field bit HasSrc0IntMods = hasIntModifiers<Src0VT>.ret;
field bit HasSrc1IntMods = hasIntModifiers<Src1VT>.ret;
field bit HasSrc2IntMods = hasIntModifiers<Src2VT>.ret;
field bit HasModifiers = HasSrc0Mods;
field bit HasOMod = HasModifiers;
field bit HasClamp = HasModifiers;
field bit HasSDWAClamp = HasSrc0;
field bit HasExt = getHasExt<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret;
@ -1073,34 +1087,6 @@ def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> {
let DstRC = RegisterOperand<VReg_64>;
}
// VOPC instructions are a special case because for the 32-bit
// encoding, we want to display the implicit vcc write as if it were
// an explicit $dst.
class VOPC_Profile<ValueType vt0, ValueType vt1 = vt0> : VOPProfile <[i1, vt0, vt1, untyped]> {
let Asm32 = "vcc, $src0, $src1";
// The destination for 32-bit encoding is implicit.
let HasDst32 = 0;
let Outs64 = (outs DstRC:$sdst);
}
class VOPC_Class_Profile<ValueType vt> : VOPC_Profile<vt, i32> {
let Ins64 = (ins Src0Mod:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
let Asm64 = "$sdst, $src0_modifiers, $src1";
let InsSDWA = (ins Src0Mod:$src0_fmodifiers, Src0RC64:$src0,
Int32InputMods:$src1_imodifiers, Src1RC64:$src1,
clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel);
let AsmSDWA = " vcc, $src0_fmodifiers, $src1_imodifiers$clamp $src0_sel $src1_sel";
}
def VOPC_I1_F32_F32 : VOPC_Profile<f32>;
def VOPC_I1_F64_F64 : VOPC_Profile<f64>;
def VOPC_I1_I32_I32 : VOPC_Profile<i32>;
def VOPC_I1_I64_I64 : VOPC_Profile<i64>;
def VOPC_I1_F32_I32 : VOPC_Class_Profile<f32>;
def VOPC_I1_F64_I32 : VOPC_Class_Profile<f64>;
def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
@ -1142,58 +1128,6 @@ def VOP_I32_F32_I32_I32 : VOPProfile <[i32, f32, i32, i32]>;
def VOP_I64_I64_I32_I64 : VOPProfile <[i64, i64, i32, i64]>;
def VOP_V4I32_I64_I32_V4I32 : VOPProfile <[v4i32, i64, i32, v4i32]>;
// This class is used only with VOPC instructions. Use $sdst for out operand
class SIInstAlias <string asm, Instruction inst, VOPProfile p,
string VariantName = ""> :
InstAlias <asm, (inst)>, PredicateControl {
field bit isCompare;
field bit isCommutable;
let ResultInst =
!if (p.HasDst32,
!if (!eq(p.NumSrcArgs, 0),
// 1 dst, 0 src
(inst p.DstRC:$sdst),
!if (!eq(p.NumSrcArgs, 1),
// 1 dst, 1 src
(inst p.DstRC:$sdst, p.Src0RC32:$src0),
!if (!eq(p.NumSrcArgs, 2),
// 1 dst, 2 src
(inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1),
// else - unreachable
(inst)))),
// else
!if (!eq(p.NumSrcArgs, 2),
// 0 dst, 2 src
(inst p.Src0RC32:$src0, p.Src1RC32:$src1),
!if (!eq(p.NumSrcArgs, 1),
// 0 dst, 1 src
(inst p.Src0RC32:$src1),
// else
// 0 dst, 0 src
(inst))));
let AsmVariantName = VariantName;
}
class SIInstAliasSI <string asm, string op_name, VOPProfile p, string VariantName = ""> :
SIInstAlias <asm, !cast<Instruction>(op_name#"_e32_si"), p, VariantName> {
let AssemblerPredicate = SIAssemblerPredicate;
}
class SIInstAliasVI <string asm, string op_name, VOPProfile p, string VariantName = ""> :
SIInstAlias <asm, !cast<Instruction>(op_name#"_e32_vi"), p, VariantName> {
let AssemblerPredicates = [isVI];
}
multiclass SIInstAliasBuilder <string asm, VOPProfile p, string VariantName = ""> {
def : SIInstAliasSI <asm, NAME, p, VariantName>;
def : SIInstAliasVI <asm, NAME, p, VariantName>;
}
class VOP <string opName> {
string OpName = opName;
}
@ -1426,26 +1360,6 @@ class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName,
let DisableDecoder = DisableVIDecoder;
}
class VOP3_C_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName,
bit HasMods = 0, bit VOP3Only = 0> :
VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>,
VOP3ce <op>,
SIMCInstr<opName#"_e64", SIEncodingFamily.SI> {
let AssemblerPredicates = [isSICI];
let DecoderNamespace = "SICI";
let DisableDecoder = DisableSIDecoder;
}
class VOP3_C_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName,
bit HasMods = 0, bit VOP3Only = 0> :
VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>,
VOP3ce_vi <op>,
SIMCInstr <opName#"_e64", SIEncodingFamily.VI> {
let AssemblerPredicates = [isVI];
let DecoderNamespace = "VI";
let DisableDecoder = DisableVIDecoder;
}
class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName,
bit HasMods = 0, bit VOP3Only = 0> :
VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>,
@ -1577,29 +1491,6 @@ multiclass VOP3e_2_3_m <vop op, dag outs, dag ins, string asm,
VOP3DisableFields<1, useSrc2Input, HasMods>;
}
multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
list<dag> pattern, string opName,
bit HasMods, bit defExec,
string revOp, list<SchedReadWrite> sched> {
def "" : VOP3_Pseudo <outs, ins, pattern, opName, HasMods>,
Commutable_REV<revOp#"_e64", !eq(revOp, opName)> {
let Defs = !if(defExec, [EXEC], []);
let SchedRW = sched;
}
def _si : VOP3_C_Real_si <op.SI3, outs, ins, asm, opName, HasMods>,
VOP3DisableFields<1, 0, HasMods> {
let Defs = !if(defExec, [EXEC], []);
let SchedRW = sched;
}
def _vi : VOP3_C_Real_vi <op.VI3, outs, ins, asm, opName, HasMods>,
VOP3DisableFields<1, 0, HasMods> {
let Defs = !if(defExec, [EXEC], []);
let SchedRW = sched;
}
}
// An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
@ -1806,169 +1697,6 @@ let isCodeGenOnly = 0 in {
} // End isCodeGenOnly = 0
}
class VOPC_Pseudo <dag ins, list<dag> pattern, string opName> :
VOPCCommon <ins, "", pattern>,
VOP <opName>,
SIMCInstr<opName#"_e32", SIEncodingFamily.NONE> {
let isPseudo = 1;
let isCodeGenOnly = 1;
}
class VOPC_SDWA <vopc op, string opName, bit DefExec, VOPProfile p> :
VOPC_SDWAe <op.VI>,
VOP_SDWA <p.OutsSDWA, p.InsSDWA, opName#p.AsmSDWA, [], p.HasModifiers>,
SDWADisableFields <p> {
let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
let hasSideEffects = DefExec;
let AsmMatchConverter = "cvtSdwaVOPC";
let AssemblerPredicates = !if(p.HasExt, [isVI], [DisableInst]);
let AsmVariantName = !if(p.HasExt, AMDGPUAsmVariants.SDWA,
AMDGPUAsmVariants.Disable);
let DecoderNamespace = "SDWA";
let DisableDecoder = DisableVIDecoder;
}
multiclass VOPC_m <vopc op, dag ins, string op_asm, list<dag> pattern,
string opName, bit DefExec, VOPProfile p,
list<SchedReadWrite> sched,
string revOpName = "", string asm = opName#"_e32 "#op_asm,
string alias_asm = opName#" "#op_asm> {
def "" : VOPC_Pseudo <ins, pattern, opName>,
Commutable_REV<revOpName#"_e32", !eq(revOpName, opName)> {
let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
let SchedRW = sched;
let isConvergent = DefExec;
}
let AssemblerPredicates = [isSICI] in {
def _si : VOPC<op.SI, ins, asm, []>,
SIMCInstr <opName#"_e32", SIEncodingFamily.SI> {
let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
let isConvergent = DefExec;
let SchedRW = sched;
let DecoderNamespace = "SICI";
let DisableDecoder = DisableSIDecoder;
}
} // End AssemblerPredicates = [isSICI]
let AssemblerPredicates = [isVI] in {
def _vi : VOPC<op.VI, ins, asm, []>,
SIMCInstr <opName#"_e32", SIEncodingFamily.VI> {
let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
let isConvergent = DefExec;
let SchedRW = sched;
let DecoderNamespace = "VI";
let DisableDecoder = DisableVIDecoder;
}
} // End AssemblerPredicates = [isVI]
defm : SIInstAliasBuilder<alias_asm, p, AMDGPUAsmVariants.Default>;
}
multiclass VOPC_Helper <vopc op, string opName, list<dag> pat32,
list<dag> pat64, bit DefExec, string revOp,
VOPProfile p, list<SchedReadWrite> sched> {
defm _e32 : VOPC_m <op, p.Ins32, p.Asm32, pat32, opName, DefExec, p, sched,
revOp>;
defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$sdst), p.Ins64, opName#p.Asm64, pat64,
opName, p.HasModifiers, DefExec, revOp, sched>;
def _sdwa : VOPC_SDWA <op, opName, DefExec, p>;
}
// Special case for class instructions which only have modifiers on
// the 1st source operand.
multiclass VOPC_Class_Helper <vopc op, string opName,
list<dag> pat64, bit DefExec, string revOp,
VOPProfile p, list<SchedReadWrite> sched> {
defm _e32 : VOPC_m <op, p.Ins32, p.Asm32, [], opName, DefExec, p, sched>;
defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$sdst), p.Ins64, opName#p.Asm64, pat64,
opName, p.HasModifiers, DefExec, revOp, sched>,
VOP3DisableModFields<1, 0, 0>;
def _sdwa : VOPC_SDWA <op, opName, DefExec, p> {
let src1_fmodifiers = 0;
let src1_imodifiers = ?;
}
}
multiclass VOPCInst <vopc op, string opName,
VOPProfile P, PatLeaf cond = COND_NULL,
string revOp = opName,
bit DefExec = 0,
list<SchedReadWrite> sched = [Write32Bit]> :
VOPC_Helper <
op, opName, [],
!if(P.HasModifiers,
[(set i1:$sdst,
(setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
i1:$clamp, i32:$omod)),
(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
cond))],
[(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
DefExec, revOp, P, sched
>;
multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
bit DefExec = 0,
list<SchedReadWrite> sched> : VOPC_Class_Helper <
op, opName,
[(set i1:$sdst,
(AMDGPUfp_class
(P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)),
P.Src1VT:$src1))],
DefExec, opName, P, sched
>;
multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
VOPCInst <op, opName, VOPC_I1_F32_F32, cond, revOp>;
multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
VOPCInst <op, opName, VOPC_I1_F64_F64, cond, revOp, 0, [WriteDoubleAdd]>;
multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
VOPCInst <op, opName, VOPC_I1_I32_I32, cond, revOp>;
multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
VOPCInst <op, opName, VOPC_I1_I64_I64, cond, revOp, 0, [Write64Bit]>;
multiclass VOPCX <vopc op, string opName, VOPProfile P,
PatLeaf cond = COND_NULL,
list<SchedReadWrite> sched,
string revOp = "">
: VOPCInst <op, opName, P, cond, revOp, 1, sched>;
multiclass VOPCX_F32 <vopc op, string opName, string revOp = opName> :
VOPCX <op, opName, VOPC_I1_F32_F32, COND_NULL, [Write32Bit], revOp>;
multiclass VOPCX_F64 <vopc op, string opName, string revOp = opName> :
VOPCX <op, opName, VOPC_I1_F64_F64, COND_NULL, [WriteDoubleAdd], revOp>;
multiclass VOPCX_I32 <vopc op, string opName, string revOp = opName> :
VOPCX <op, opName, VOPC_I1_I32_I32, COND_NULL, [Write32Bit], revOp>;
multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> :
VOPCX <op, opName, VOPC_I1_I64_I64, COND_NULL, [Write64Bit], revOp>;
multiclass VOPC_CLASS_F32 <vopc op, string opName> :
VOPCClassInst <op, opName, VOPC_I1_F32_I32, 0, [Write32Bit]>;
multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
VOPCClassInst <op, opName, VOPC_I1_F32_I32, 1, [Write32Bit]>;
multiclass VOPC_CLASS_F64 <vopc op, string opName> :
VOPCClassInst <op, opName, VOPC_I1_F64_I32, 0, [WriteDoubleAdd]>;
multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
VOPCClassInst <op, opName, VOPC_I1_F64_I32, 1, [WriteDoubleAdd]>;
multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
list<dag> pat, int NumSrcArgs, bit HasMods,
bit VOP3Only = 0> : VOP3_m <

304
lib/Target/AMDGPU/SIInstructions.td
View File

@ -21,6 +21,7 @@ def isSI : Predicate<"Subtarget->getGeneration() "
def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
include "VOPInstructions.td"
include "SOPInstructions.td"
include "SMInstructions.td"
include "FLATInstructions.td"
@ -34,244 +35,6 @@ let SubtargetPredicate = isGCN in {
defm EXP : EXP_m;
//===----------------------------------------------------------------------===//
// VOPC Instructions
//===----------------------------------------------------------------------===//
let isCompare = 1, isCommutable = 1 in {
defm V_CMP_F_F32 : VOPC_F32 <vopc<0x0, 0x40>, "v_cmp_f_f32">;
defm V_CMP_LT_F32 : VOPC_F32 <vopc<0x1, 0x41>, "v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">;
defm V_CMP_EQ_F32 : VOPC_F32 <vopc<0x2, 0x42>, "v_cmp_eq_f32", COND_OEQ>;
defm V_CMP_LE_F32 : VOPC_F32 <vopc<0x3, 0x43>, "v_cmp_le_f32", COND_OLE, "v_cmp_ge_f32">;
defm V_CMP_GT_F32 : VOPC_F32 <vopc<0x4, 0x44>, "v_cmp_gt_f32", COND_OGT>;
defm V_CMP_LG_F32 : VOPC_F32 <vopc<0x5, 0x45>, "v_cmp_lg_f32", COND_ONE>;
defm V_CMP_GE_F32 : VOPC_F32 <vopc<0x6, 0x46>, "v_cmp_ge_f32", COND_OGE>;
defm V_CMP_O_F32 : VOPC_F32 <vopc<0x7, 0x47>, "v_cmp_o_f32", COND_O>;
defm V_CMP_U_F32 : VOPC_F32 <vopc<0x8, 0x48>, "v_cmp_u_f32", COND_UO>;
defm V_CMP_NGE_F32 : VOPC_F32 <vopc<0x9, 0x49>, "v_cmp_nge_f32", COND_ULT, "v_cmp_nle_f32">;
defm V_CMP_NLG_F32 : VOPC_F32 <vopc<0xa, 0x4a>, "v_cmp_nlg_f32", COND_UEQ>;
defm V_CMP_NGT_F32 : VOPC_F32 <vopc<0xb, 0x4b>, "v_cmp_ngt_f32", COND_ULE, "v_cmp_nlt_f32">;
defm V_CMP_NLE_F32 : VOPC_F32 <vopc<0xc, 0x4c>, "v_cmp_nle_f32", COND_UGT>;
defm V_CMP_NEQ_F32 : VOPC_F32 <vopc<0xd, 0x4d>, "v_cmp_neq_f32", COND_UNE>;
defm V_CMP_NLT_F32 : VOPC_F32 <vopc<0xe, 0x4e>, "v_cmp_nlt_f32", COND_UGE>;
defm V_CMP_TRU_F32 : VOPC_F32 <vopc<0xf, 0x4f>, "v_cmp_tru_f32">;
defm V_CMPX_F_F32 : VOPCX_F32 <vopc<0x10, 0x50>, "v_cmpx_f_f32">;
defm V_CMPX_LT_F32 : VOPCX_F32 <vopc<0x11, 0x51>, "v_cmpx_lt_f32", "v_cmpx_gt_f32">;
defm V_CMPX_EQ_F32 : VOPCX_F32 <vopc<0x12, 0x52>, "v_cmpx_eq_f32">;
defm V_CMPX_LE_F32 : VOPCX_F32 <vopc<0x13, 0x53>, "v_cmpx_le_f32", "v_cmpx_ge_f32">;
defm V_CMPX_GT_F32 : VOPCX_F32 <vopc<0x14, 0x54>, "v_cmpx_gt_f32">;
defm V_CMPX_LG_F32 : VOPCX_F32 <vopc<0x15, 0x55>, "v_cmpx_lg_f32">;
defm V_CMPX_GE_F32 : VOPCX_F32 <vopc<0x16, 0x56>, "v_cmpx_ge_f32">;
defm V_CMPX_O_F32 : VOPCX_F32 <vopc<0x17, 0x57>, "v_cmpx_o_f32">;
defm V_CMPX_U_F32 : VOPCX_F32 <vopc<0x18, 0x58>, "v_cmpx_u_f32">;
defm V_CMPX_NGE_F32 : VOPCX_F32 <vopc<0x19, 0x59>, "v_cmpx_nge_f32">;
defm V_CMPX_NLG_F32 : VOPCX_F32 <vopc<0x1a, 0x5a>, "v_cmpx_nlg_f32">;
defm V_CMPX_NGT_F32 : VOPCX_F32 <vopc<0x1b, 0x5b>, "v_cmpx_ngt_f32">;
defm V_CMPX_NLE_F32 : VOPCX_F32 <vopc<0x1c, 0x5c>, "v_cmpx_nle_f32">;
defm V_CMPX_NEQ_F32 : VOPCX_F32 <vopc<0x1d, 0x5d>, "v_cmpx_neq_f32">;
defm V_CMPX_NLT_F32 : VOPCX_F32 <vopc<0x1e, 0x5e>, "v_cmpx_nlt_f32">;
defm V_CMPX_TRU_F32 : VOPCX_F32 <vopc<0x1f, 0x5f>, "v_cmpx_tru_f32">;
defm V_CMP_F_F64 : VOPC_F64 <vopc<0x20, 0x60>, "v_cmp_f_f64">;
defm V_CMP_LT_F64 : VOPC_F64 <vopc<0x21, 0x61>, "v_cmp_lt_f64", COND_OLT, "v_cmp_gt_f64">;
defm V_CMP_EQ_F64 : VOPC_F64 <vopc<0x22, 0x62>, "v_cmp_eq_f64", COND_OEQ>;
defm V_CMP_LE_F64 : VOPC_F64 <vopc<0x23, 0x63>, "v_cmp_le_f64", COND_OLE, "v_cmp_ge_f64">;
defm V_CMP_GT_F64 : VOPC_F64 <vopc<0x24, 0x64>, "v_cmp_gt_f64", COND_OGT>;
defm V_CMP_LG_F64 : VOPC_F64 <vopc<0x25, 0x65>, "v_cmp_lg_f64", COND_ONE>;
defm V_CMP_GE_F64 : VOPC_F64 <vopc<0x26, 0x66>, "v_cmp_ge_f64", COND_OGE>;
defm V_CMP_O_F64 : VOPC_F64 <vopc<0x27, 0x67>, "v_cmp_o_f64", COND_O>;
defm V_CMP_U_F64 : VOPC_F64 <vopc<0x28, 0x68>, "v_cmp_u_f64", COND_UO>;
defm V_CMP_NGE_F64 : VOPC_F64 <vopc<0x29, 0x69>, "v_cmp_nge_f64", COND_ULT, "v_cmp_nle_f64">;
defm V_CMP_NLG_F64 : VOPC_F64 <vopc<0x2a, 0x6a>, "v_cmp_nlg_f64", COND_UEQ>;
defm V_CMP_NGT_F64 : VOPC_F64 <vopc<0x2b, 0x6b>, "v_cmp_ngt_f64", COND_ULE, "v_cmp_nlt_f64">;
defm V_CMP_NLE_F64 : VOPC_F64 <vopc<0x2c, 0x6c>, "v_cmp_nle_f64", COND_UGT>;
defm V_CMP_NEQ_F64 : VOPC_F64 <vopc<0x2d, 0x6d>, "v_cmp_neq_f64", COND_UNE>;
defm V_CMP_NLT_F64 : VOPC_F64 <vopc<0x2e, 0x6e>, "v_cmp_nlt_f64", COND_UGE>;
defm V_CMP_TRU_F64 : VOPC_F64 <vopc<0x2f, 0x6f>, "v_cmp_tru_f64">;
defm V_CMPX_F_F64 : VOPCX_F64 <vopc<0x30, 0x70>, "v_cmpx_f_f64">;
defm V_CMPX_LT_F64 : VOPCX_F64 <vopc<0x31, 0x71>, "v_cmpx_lt_f64", "v_cmpx_gt_f64">;
defm V_CMPX_EQ_F64 : VOPCX_F64 <vopc<0x32, 0x72>, "v_cmpx_eq_f64">;
defm V_CMPX_LE_F64 : VOPCX_F64 <vopc<0x33, 0x73>, "v_cmpx_le_f64", "v_cmpx_ge_f64">;
defm V_CMPX_GT_F64 : VOPCX_F64 <vopc<0x34, 0x74>, "v_cmpx_gt_f64">;
defm V_CMPX_LG_F64 : VOPCX_F64 <vopc<0x35, 0x75>, "v_cmpx_lg_f64">;
defm V_CMPX_GE_F64 : VOPCX_F64 <vopc<0x36, 0x76>, "v_cmpx_ge_f64">;
defm V_CMPX_O_F64 : VOPCX_F64 <vopc<0x37, 0x77>, "v_cmpx_o_f64">;
defm V_CMPX_U_F64 : VOPCX_F64 <vopc<0x38, 0x78>, "v_cmpx_u_f64">;
defm V_CMPX_NGE_F64 : VOPCX_F64 <vopc<0x39, 0x79>, "v_cmpx_nge_f64", "v_cmpx_nle_f64">;
defm V_CMPX_NLG_F64 : VOPCX_F64 <vopc<0x3a, 0x7a>, "v_cmpx_nlg_f64">;
defm V_CMPX_NGT_F64 : VOPCX_F64 <vopc<0x3b, 0x7b>, "v_cmpx_ngt_f64", "v_cmpx_nlt_f64">;
defm V_CMPX_NLE_F64 : VOPCX_F64 <vopc<0x3c, 0x7c>, "v_cmpx_nle_f64">;
defm V_CMPX_NEQ_F64 : VOPCX_F64 <vopc<0x3d, 0x7d>, "v_cmpx_neq_f64">;
defm V_CMPX_NLT_F64 : VOPCX_F64 <vopc<0x3e, 0x7e>, "v_cmpx_nlt_f64">;
defm V_CMPX_TRU_F64 : VOPCX_F64 <vopc<0x3f, 0x7f>, "v_cmpx_tru_f64">;
let SubtargetPredicate = isSICI in {
defm V_CMPS_F_F32 : VOPC_F32 <vopc<0x40>, "v_cmps_f_f32">;
defm V_CMPS_LT_F32 : VOPC_F32 <vopc<0x41>, "v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">;
defm V_CMPS_EQ_F32 : VOPC_F32 <vopc<0x42>, "v_cmps_eq_f32">;
defm V_CMPS_LE_F32 : VOPC_F32 <vopc<0x43>, "v_cmps_le_f32", COND_NULL, "v_cmps_ge_f32">;
defm V_CMPS_GT_F32 : VOPC_F32 <vopc<0x44>, "v_cmps_gt_f32">;
defm V_CMPS_LG_F32 : VOPC_F32 <vopc<0x45>, "v_cmps_lg_f32">;
defm V_CMPS_GE_F32 : VOPC_F32 <vopc<0x46>, "v_cmps_ge_f32">;
defm V_CMPS_O_F32 : VOPC_F32 <vopc<0x47>, "v_cmps_o_f32">;
defm V_CMPS_U_F32 : VOPC_F32 <vopc<0x48>, "v_cmps_u_f32">;
defm V_CMPS_NGE_F32 : VOPC_F32 <vopc<0x49>, "v_cmps_nge_f32", COND_NULL, "v_cmps_nle_f32">;
defm V_CMPS_NLG_F32 : VOPC_F32 <vopc<0x4a>, "v_cmps_nlg_f32">;
defm V_CMPS_NGT_F32 : VOPC_F32 <vopc<0x4b>, "v_cmps_ngt_f32", COND_NULL, "v_cmps_nlt_f32">;
defm V_CMPS_NLE_F32 : VOPC_F32 <vopc<0x4c>, "v_cmps_nle_f32">;
defm V_CMPS_NEQ_F32 : VOPC_F32 <vopc<0x4d>, "v_cmps_neq_f32">;
defm V_CMPS_NLT_F32 : VOPC_F32 <vopc<0x4e>, "v_cmps_nlt_f32">;
defm V_CMPS_TRU_F32 : VOPC_F32 <vopc<0x4f>, "v_cmps_tru_f32">;
defm V_CMPSX_F_F32 : VOPCX_F32 <vopc<0x50>, "v_cmpsx_f_f32">;
defm V_CMPSX_LT_F32 : VOPCX_F32 <vopc<0x51>, "v_cmpsx_lt_f32", "v_cmpsx_gt_f32">;
defm V_CMPSX_EQ_F32 : VOPCX_F32 <vopc<0x52>, "v_cmpsx_eq_f32">;
defm V_CMPSX_LE_F32 : VOPCX_F32 <vopc<0x53>, "v_cmpsx_le_f32", "v_cmpsx_ge_f32">;
defm V_CMPSX_GT_F32 : VOPCX_F32 <vopc<0x54>, "v_cmpsx_gt_f32">;
defm V_CMPSX_LG_F32 : VOPCX_F32 <vopc<0x55>, "v_cmpsx_lg_f32">;
defm V_CMPSX_GE_F32 : VOPCX_F32 <vopc<0x56>, "v_cmpsx_ge_f32">;
defm V_CMPSX_O_F32 : VOPCX_F32 <vopc<0x57>, "v_cmpsx_o_f32">;
defm V_CMPSX_U_F32 : VOPCX_F32 <vopc<0x58>, "v_cmpsx_u_f32">;
defm V_CMPSX_NGE_F32 : VOPCX_F32 <vopc<0x59>, "v_cmpsx_nge_f32", "v_cmpsx_nle_f32">;
defm V_CMPSX_NLG_F32 : VOPCX_F32 <vopc<0x5a>, "v_cmpsx_nlg_f32">;
defm V_CMPSX_NGT_F32 : VOPCX_F32 <vopc<0x5b>, "v_cmpsx_ngt_f32", "v_cmpsx_nlt_f32">;
defm V_CMPSX_NLE_F32 : VOPCX_F32 <vopc<0x5c>, "v_cmpsx_nle_f32">;
defm V_CMPSX_NEQ_F32 : VOPCX_F32 <vopc<0x5d>, "v_cmpsx_neq_f32">;
defm V_CMPSX_NLT_F32 : VOPCX_F32 <vopc<0x5e>, "v_cmpsx_nlt_f32">;
defm V_CMPSX_TRU_F32 : VOPCX_F32 <vopc<0x5f>, "v_cmpsx_tru_f32">;
defm V_CMPS_F_F64 : VOPC_F64 <vopc<0x60>, "v_cmps_f_f64">;
defm V_CMPS_LT_F64 : VOPC_F64 <vopc<0x61>, "v_cmps_lt_f64", COND_NULL, "v_cmps_gt_f64">;
defm V_CMPS_EQ_F64 : VOPC_F64 <vopc<0x62>, "v_cmps_eq_f64">;
defm V_CMPS_LE_F64 : VOPC_F64 <vopc<0x63>, "v_cmps_le_f64", COND_NULL, "v_cmps_ge_f64">;
defm V_CMPS_GT_F64 : VOPC_F64 <vopc<0x64>, "v_cmps_gt_f64">;
defm V_CMPS_LG_F64 : VOPC_F64 <vopc<0x65>, "v_cmps_lg_f64">;
defm V_CMPS_GE_F64 : VOPC_F64 <vopc<0x66>, "v_cmps_ge_f64">;
defm V_CMPS_O_F64 : VOPC_F64 <vopc<0x67>, "v_cmps_o_f64">;
defm V_CMPS_U_F64 : VOPC_F64 <vopc<0x68>, "v_cmps_u_f64">;
defm V_CMPS_NGE_F64 : VOPC_F64 <vopc<0x69>, "v_cmps_nge_f64", COND_NULL, "v_cmps_nle_f64">;
defm V_CMPS_NLG_F64 : VOPC_F64 <vopc<0x6a>, "v_cmps_nlg_f64">;
defm V_CMPS_NGT_F64 : VOPC_F64 <vopc<0x6b>, "v_cmps_ngt_f64", COND_NULL, "v_cmps_nlt_f64">;
defm V_CMPS_NLE_F64 : VOPC_F64 <vopc<0x6c>, "v_cmps_nle_f64">;
defm V_CMPS_NEQ_F64 : VOPC_F64 <vopc<0x6d>, "v_cmps_neq_f64">;
defm V_CMPS_NLT_F64 : VOPC_F64 <vopc<0x6e>, "v_cmps_nlt_f64">;
defm V_CMPS_TRU_F64 : VOPC_F64 <vopc<0x6f>, "v_cmps_tru_f64">;
defm V_CMPSX_F_F64 : VOPCX_F64 <vopc<0x70>, "v_cmpsx_f_f64">;
defm V_CMPSX_LT_F64 : VOPCX_F64 <vopc<0x71>, "v_cmpsx_lt_f64", "v_cmpsx_gt_f64">;
defm V_CMPSX_EQ_F64 : VOPCX_F64 <vopc<0x72>, "v_cmpsx_eq_f64">;
defm V_CMPSX_LE_F64 : VOPCX_F64 <vopc<0x73>, "v_cmpsx_le_f64", "v_cmpsx_ge_f64">;
defm V_CMPSX_GT_F64 : VOPCX_F64 <vopc<0x74>, "v_cmpsx_gt_f64">;
defm V_CMPSX_LG_F64 : VOPCX_F64 <vopc<0x75>, "v_cmpsx_lg_f64">;
defm V_CMPSX_GE_F64 : VOPCX_F64 <vopc<0x76>, "v_cmpsx_ge_f64">;
defm V_CMPSX_O_F64 : VOPCX_F64 <vopc<0x77>, "v_cmpsx_o_f64">;
defm V_CMPSX_U_F64 : VOPCX_F64 <vopc<0x78>, "v_cmpsx_u_f64">;
defm V_CMPSX_NGE_F64 : VOPCX_F64 <vopc<0x79>, "v_cmpsx_nge_f64", "v_cmpsx_nle_f64">;
defm V_CMPSX_NLG_F64 : VOPCX_F64 <vopc<0x7a>, "v_cmpsx_nlg_f64">;
defm V_CMPSX_NGT_F64 : VOPCX_F64 <vopc<0x7b>, "v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">;
defm V_CMPSX_NLE_F64 : VOPCX_F64 <vopc<0x7c>, "v_cmpsx_nle_f64">;
defm V_CMPSX_NEQ_F64 : VOPCX_F64 <vopc<0x7d>, "v_cmpsx_neq_f64">;
defm V_CMPSX_NLT_F64 : VOPCX_F64 <vopc<0x7e>, "v_cmpsx_nlt_f64">;
defm V_CMPSX_TRU_F64 : VOPCX_F64 <vopc<0x7f>, "v_cmpsx_tru_f64">;
} // End SubtargetPredicate = isSICI
defm V_CMP_F_I32 : VOPC_I32 <vopc<0x80, 0xc0>, "v_cmp_f_i32">;
defm V_CMP_LT_I32 : VOPC_I32 <vopc<0x81, 0xc1>, "v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">;
defm V_CMP_EQ_I32 : VOPC_I32 <vopc<0x82, 0xc2>, "v_cmp_eq_i32", COND_EQ>;
defm V_CMP_LE_I32 : VOPC_I32 <vopc<0x83, 0xc3>, "v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">;
defm V_CMP_GT_I32 : VOPC_I32 <vopc<0x84, 0xc4>, "v_cmp_gt_i32", COND_SGT>;
defm V_CMP_NE_I32 : VOPC_I32 <vopc<0x85, 0xc5>, "v_cmp_ne_i32", COND_NE>;
defm V_CMP_GE_I32 : VOPC_I32 <vopc<0x86, 0xc6>, "v_cmp_ge_i32", COND_SGE>;
defm V_CMP_T_I32 : VOPC_I32 <vopc<0x87, 0xc7>, "v_cmp_t_i32">;
defm V_CMPX_F_I32 : VOPCX_I32 <vopc<0x90, 0xd0>, "v_cmpx_f_i32">;
defm V_CMPX_LT_I32 : VOPCX_I32 <vopc<0x91, 0xd1>, "v_cmpx_lt_i32", "v_cmpx_gt_i32">;
defm V_CMPX_EQ_I32 : VOPCX_I32 <vopc<0x92, 0xd2>, "v_cmpx_eq_i32">;
defm V_CMPX_LE_I32 : VOPCX_I32 <vopc<0x93, 0xd3>, "v_cmpx_le_i32", "v_cmpx_ge_i32">;
defm V_CMPX_GT_I32 : VOPCX_I32 <vopc<0x94, 0xd4>, "v_cmpx_gt_i32">;
defm V_CMPX_NE_I32 : VOPCX_I32 <vopc<0x95, 0xd5>, "v_cmpx_ne_i32">;
defm V_CMPX_GE_I32 : VOPCX_I32 <vopc<0x96, 0xd6>, "v_cmpx_ge_i32">;
defm V_CMPX_T_I32 : VOPCX_I32 <vopc<0x97, 0xd7>, "v_cmpx_t_i32">;
defm V_CMP_F_I64 : VOPC_I64 <vopc<0xa0, 0xe0>, "v_cmp_f_i64">;
defm V_CMP_LT_I64 : VOPC_I64 <vopc<0xa1, 0xe1>, "v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">;
defm V_CMP_EQ_I64 : VOPC_I64 <vopc<0xa2, 0xe2>, "v_cmp_eq_i64", COND_EQ>;
defm V_CMP_LE_I64 : VOPC_I64 <vopc<0xa3, 0xe3>, "v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">;
defm V_CMP_GT_I64 : VOPC_I64 <vopc<0xa4, 0xe4>, "v_cmp_gt_i64", COND_SGT>;
defm V_CMP_NE_I64 : VOPC_I64 <vopc<0xa5, 0xe5>, "v_cmp_ne_i64", COND_NE>;
defm V_CMP_GE_I64 : VOPC_I64 <vopc<0xa6, 0xe6>, "v_cmp_ge_i64", COND_SGE>;
defm V_CMP_T_I64 : VOPC_I64 <vopc<0xa7, 0xe7>, "v_cmp_t_i64">;
defm V_CMPX_F_I64 : VOPCX_I64 <vopc<0xb0, 0xf0>, "v_cmpx_f_i64">;
defm V_CMPX_LT_I64 : VOPCX_I64 <vopc<0xb1, 0xf1>, "v_cmpx_lt_i64", "v_cmpx_gt_i64">;
defm V_CMPX_EQ_I64 : VOPCX_I64 <vopc<0xb2, 0xf2>, "v_cmpx_eq_i64">;
defm V_CMPX_LE_I64 : VOPCX_I64 <vopc<0xb3, 0xf3>, "v_cmpx_le_i64", "v_cmpx_ge_i64">;
defm V_CMPX_GT_I64 : VOPCX_I64 <vopc<0xb4, 0xf4>, "v_cmpx_gt_i64">;
defm V_CMPX_NE_I64 : VOPCX_I64 <vopc<0xb5, 0xf5>, "v_cmpx_ne_i64">;
defm V_CMPX_GE_I64 : VOPCX_I64 <vopc<0xb6, 0xf6>, "v_cmpx_ge_i64">;
defm V_CMPX_T_I64 : VOPCX_I64 <vopc<0xb7, 0xf7>, "v_cmpx_t_i64">;
defm V_CMP_F_U32 : VOPC_I32 <vopc<0xc0, 0xc8>, "v_cmp_f_u32">;
defm V_CMP_LT_U32 : VOPC_I32 <vopc<0xc1, 0xc9>, "v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">;
defm V_CMP_EQ_U32 : VOPC_I32 <vopc<0xc2, 0xca>, "v_cmp_eq_u32", COND_EQ>;
defm V_CMP_LE_U32 : VOPC_I32 <vopc<0xc3, 0xcb>, "v_cmp_le_u32", COND_ULE, "v_cmp_ge_u32">;
defm V_CMP_GT_U32 : VOPC_I32 <vopc<0xc4, 0xcc>, "v_cmp_gt_u32", COND_UGT>;
defm V_CMP_NE_U32 : VOPC_I32 <vopc<0xc5, 0xcd>, "v_cmp_ne_u32", COND_NE>;
defm V_CMP_GE_U32 : VOPC_I32 <vopc<0xc6, 0xce>, "v_cmp_ge_u32", COND_UGE>;
defm V_CMP_T_U32 : VOPC_I32 <vopc<0xc7, 0xcf>, "v_cmp_t_u32">;
defm V_CMPX_F_U32 : VOPCX_I32 <vopc<0xd0, 0xd8>, "v_cmpx_f_u32">;
defm V_CMPX_LT_U32 : VOPCX_I32 <vopc<0xd1, 0xd9>, "v_cmpx_lt_u32", "v_cmpx_gt_u32">;
defm V_CMPX_EQ_U32 : VOPCX_I32 <vopc<0xd2, 0xda>, "v_cmpx_eq_u32">;
defm V_CMPX_LE_U32 : VOPCX_I32 <vopc<0xd3, 0xdb>, "v_cmpx_le_u32", "v_cmpx_le_u32">;
defm V_CMPX_GT_U32 : VOPCX_I32 <vopc<0xd4, 0xdc>, "v_cmpx_gt_u32">;
defm V_CMPX_NE_U32 : VOPCX_I32 <vopc<0xd5, 0xdd>, "v_cmpx_ne_u32">;
defm V_CMPX_GE_U32 : VOPCX_I32 <vopc<0xd6, 0xde>, "v_cmpx_ge_u32">;
defm V_CMPX_T_U32 : VOPCX_I32 <vopc<0xd7, 0xdf>, "v_cmpx_t_u32">;
defm V_CMP_F_U64 : VOPC_I64 <vopc<0xe0, 0xe8>, "v_cmp_f_u64">;
defm V_CMP_LT_U64 : VOPC_I64 <vopc<0xe1, 0xe9>, "v_cmp_lt_u64", COND_ULT, "v_cmp_gt_u64">;
defm V_CMP_EQ_U64 : VOPC_I64 <vopc<0xe2, 0xea>, "v_cmp_eq_u64", COND_EQ>;
defm V_CMP_LE_U64 : VOPC_I64 <vopc<0xe3, 0xeb>, "v_cmp_le_u64", COND_ULE, "v_cmp_ge_u64">;
defm V_CMP_GT_U64 : VOPC_I64 <vopc<0xe4, 0xec>, "v_cmp_gt_u64", COND_UGT>;
defm V_CMP_NE_U64 : VOPC_I64 <vopc<0xe5, 0xed>, "v_cmp_ne_u64", COND_NE>;
defm V_CMP_GE_U64 : VOPC_I64 <vopc<0xe6, 0xee>, "v_cmp_ge_u64", COND_UGE>;
defm V_CMP_T_U64 : VOPC_I64 <vopc<0xe7, 0xef>, "v_cmp_t_u64">;
defm V_CMPX_F_U64 : VOPCX_I64 <vopc<0xf0, 0xf8>, "v_cmpx_f_u64">;
defm V_CMPX_LT_U64 : VOPCX_I64 <vopc<0xf1, 0xf9>, "v_cmpx_lt_u64", "v_cmpx_gt_u64">;
defm V_CMPX_EQ_U64 : VOPCX_I64 <vopc<0xf2, 0xfa>, "v_cmpx_eq_u64">;
defm V_CMPX_LE_U64 : VOPCX_I64 <vopc<0xf3, 0xfb>, "v_cmpx_le_u64", "v_cmpx_ge_u64">;
defm V_CMPX_GT_U64 : VOPCX_I64 <vopc<0xf4, 0xfc>, "v_cmpx_gt_u64">;
defm V_CMPX_NE_U64 : VOPCX_I64 <vopc<0xf5, 0xfd>, "v_cmpx_ne_u64">;
defm V_CMPX_GE_U64 : VOPCX_I64 <vopc<0xf6, 0xfe>, "v_cmpx_ge_u64">;
defm V_CMPX_T_U64 : VOPCX_I64 <vopc<0xf7, 0xff>, "v_cmpx_t_u64">;
} // End isCompare = 1, isCommutable = 1
defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <vopc<0x88, 0x10>, "v_cmp_class_f32">;
defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <vopc<0x98, 0x11>, "v_cmpx_class_f32">;
defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <vopc<0xa8, 0x12>, "v_cmp_class_f64">;
defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <vopc<0xb8, 0x13>, "v_cmpx_class_f64">;
//===----------------------------------------------------------------------===//
// VOP1 Instructions
//===----------------------------------------------------------------------===//
@ -1266,71 +1029,6 @@ def : Pat <
$src0, $src1, $src2, $src3)
>;
//===----------------------------------------------------------------------===//
// V_ICMPIntrinsic Pattern.
//===----------------------------------------------------------------------===//
class ICMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> : Pat <
(AMDGPUsetcc vt:$src0, vt:$src1, cond),
(inst $src0, $src1)
>;
def : ICMP_Pattern <COND_EQ, V_CMP_EQ_I32_e64, i32>;
def : ICMP_Pattern <COND_NE, V_CMP_NE_I32_e64, i32>;
def : ICMP_Pattern <COND_UGT, V_CMP_GT_U32_e64, i32>;
def : ICMP_Pattern <COND_UGE, V_CMP_GE_U32_e64, i32>;
def : ICMP_Pattern <COND_ULT, V_CMP_LT_U32_e64, i32>;
def : ICMP_Pattern <COND_ULE, V_CMP_LE_U32_e64, i32>;
def : ICMP_Pattern <COND_SGT, V_CMP_GT_I32_e64, i32>;
def : ICMP_Pattern <COND_SGE, V_CMP_GE_I32_e64, i32>;
def : ICMP_Pattern <COND_SLT, V_CMP_LT_I32_e64, i32>;
def : ICMP_Pattern <COND_SLE, V_CMP_LE_I32_e64, i32>;
def : ICMP_Pattern <COND_EQ, V_CMP_EQ_I64_e64, i64>;
def : ICMP_Pattern <COND_NE, V_CMP_NE_I64_e64, i64>;
def : ICMP_Pattern <COND_UGT, V_CMP_GT_U64_e64, i64>;
def : ICMP_Pattern <COND_UGE, V_CMP_GE_U64_e64, i64>;
def : ICMP_Pattern <COND_ULT, V_CMP_LT_U64_e64, i64>;
def : ICMP_Pattern <COND_ULE, V_CMP_LE_U64_e64, i64>;
def : ICMP_Pattern <COND_SGT, V_CMP_GT_I64_e64, i64>;
def : ICMP_Pattern <COND_SGE, V_CMP_GE_I64_e64, i64>;
def : ICMP_Pattern <COND_SLT, V_CMP_LT_I64_e64, i64>;
def : ICMP_Pattern <COND_SLE, V_CMP_LE_I64_e64, i64>;
class FCMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> : Pat <
(i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
(vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),
(inst $src0_modifiers, $src0, $src1_modifiers, $src1,
DSTCLAMP.NONE, DSTOMOD.NONE)
>;
def : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F32_e64, f32>;
def : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F32_e64, f32>;
def : FCMP_Pattern <COND_OGT, V_CMP_GT_F32_e64, f32>;
def : FCMP_Pattern <COND_OGE, V_CMP_GE_F32_e64, f32>;
def : FCMP_Pattern <COND_OLT, V_CMP_LT_F32_e64, f32>;
def : FCMP_Pattern <COND_OLE, V_CMP_LE_F32_e64, f32>;
def : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F64_e64, f64>;
def : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F64_e64, f64>;
def : FCMP_Pattern <COND_OGT, V_CMP_GT_F64_e64, f64>;
def : FCMP_Pattern <COND_OGE, V_CMP_GE_F64_e64, f64>;
def : FCMP_Pattern <COND_OLT, V_CMP_LT_F64_e64, f64>;
def : FCMP_Pattern <COND_OLE, V_CMP_LE_F64_e64, f64>;
def : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F32_e64, f32>;
def : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F32_e64, f32>;
def : FCMP_Pattern <COND_UGT, V_CMP_NLE_F32_e64, f32>;
def : FCMP_Pattern <COND_UGE, V_CMP_NLT_F32_e64, f32>;
def : FCMP_Pattern <COND_ULT, V_CMP_NGE_F32_e64, f32>;
def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F32_e64, f32>;
def : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F64_e64, f64>;
def : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F64_e64, f64>;
def : FCMP_Pattern <COND_UGT, V_CMP_NLE_F64_e64, f64>;
def : FCMP_Pattern <COND_UGE, V_CMP_NLT_F64_e64, f64>;
def : FCMP_Pattern <COND_ULT, V_CMP_NGE_F64_e64, f64>;
def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F64_e64, f64>;
//===----------------------------------------------------------------------===//
// VOP1 Patterns
//===----------------------------------------------------------------------===//

21
lib/Target/AMDGPU/VIInstrFormats.td
View File

@ -42,14 +42,6 @@ class VOP3e_vi <bits<10> op> : VOP3a_vi <op> {
let Inst{7-0} = vdst;
}
// Encoding used for VOPC instructions encoded as VOP3
// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
class VOP3ce_vi <bits<10> op> : VOP3a_vi <op> {
bits<8> sdst;
let Inst{7-0} = sdst;
}
class VOP3be_vi <bits<10> op> : Enc64 {
bits<8> vdst;
bits<2> src0_modifiers;
@ -176,19 +168,6 @@ class VOP2_SDWAe <bits<6> op> : VOP_SDWAe {
let Inst{31} = 0x0; // encoding
}
class VOPC_SDWAe <bits<8> op> : VOP_SDWAe {
bits<8> src1;
let Inst{8-0} = 0xf9; // sdwa
let Inst{16-9} = src1;
let Inst{24-17} = op;
let Inst{31-25} = 0x3e; // encoding
// VOPC disallows dst_sel and dst_unused as they have no effect on destination
let Inst{42-40} = 0x6;
let Inst{44-43} = 0x2;
}
class EXPe_vi : EXPe {
let Inst{31-26} = 0x31; //encoding
}

964
lib/Target/AMDGPU/VOPCInstructions.td Normal file
View File

@ -0,0 +1,964 @@
//===-- VOPCInstructions.td - Vector Instruction Defintions ---------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Encodings
//===----------------------------------------------------------------------===//
class VOPCe <bits<8> op> : Enc32 {
bits<9> src0;
bits<8> src1;
let Inst{8-0} = src0;
let Inst{16-9} = src1;
let Inst{24-17} = op;
let Inst{31-25} = 0x3e;
}
//===----------------------------------------------------------------------===//
// VOPC classes
//===----------------------------------------------------------------------===//
// VOPC instructions are a special case because for the 32-bit
// encoding, we want to display the implicit vcc write as if it were
// an explicit $dst.
class VOPC_Profile<list<SchedReadWrite> sched, ValueType vt0, ValueType vt1 = vt0> :
VOPProfile <[i1, vt0, vt1, untyped]> {
let Asm32 = "vcc, $src0, $src1";
// The destination for 32-bit encoding is implicit.
let HasDst32 = 0;
let Outs64 = (outs VOPDstS64:$sdst);
list<SchedReadWrite> Schedule = sched;
}
class VOPC_Pseudo <string opName, VOPC_Profile P, list<dag> pattern=[]> :
InstSI<(outs), P.Ins32, "", pattern>,
VOP <opName>,
SIMCInstr<opName#"_e32", SIEncodingFamily.NONE> {
let isPseudo = 1;
let isCodeGenOnly = 1;
let UseNamedOperandTable = 1;
string Mnemonic = opName;
string AsmOperands = P.Asm32;
let Size = 4;
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let VALU = 1;
let VOPC = 1;
let Uses = [EXEC];
let Defs = [VCC];
let SubtargetPredicate = isGCN;
VOPProfile Pfl = P;
}
class VOPC_Real <VOPC_Pseudo ps, int EncodingFamily> :
InstSI <ps.OutOperandList, ps.InOperandList, ps.PseudoInstr # " " # ps.AsmOperands, []>,
SIMCInstr <ps.PseudoInstr, EncodingFamily> {
let isPseudo = 0;
let isCodeGenOnly = 0;
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
let Constraints = ps.Constraints;
let DisableEncoding = ps.DisableEncoding;
let TSFlags = ps.TSFlags;
}
// This class is used only with VOPC instructions. Use $sdst for out operand
class VOPCInstAlias <VOP3_PseudoNew ps, Instruction inst, VOPProfile p = ps.Pfl> :
InstAlias <ps.OpName#" "#p.Asm32, (inst)>, PredicateControl {
field bit isCompare;
field bit isCommutable;
let ResultInst =
!if (p.HasDst32,
!if (!eq(p.NumSrcArgs, 0),
// 1 dst, 0 src
(inst p.DstRC:$sdst),
!if (!eq(p.NumSrcArgs, 1),
// 1 dst, 1 src
(inst p.DstRC:$sdst, p.Src0RC32:$src0),
!if (!eq(p.NumSrcArgs, 2),
// 1 dst, 2 src
(inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1),
// else - unreachable
(inst)))),
// else
!if (!eq(p.NumSrcArgs, 2),
// 0 dst, 2 src
(inst p.Src0RC32:$src0, p.Src1RC32:$src1),
!if (!eq(p.NumSrcArgs, 1),
// 0 dst, 1 src
(inst p.Src0RC32:$src1),
// else
// 0 dst, 0 src
(inst))));
let AsmVariantName = AMDGPUAsmVariants.Default;
let SubtargetPredicate = AssemblerPredicate;
}
multiclass VOPC_Pseudos <string opName,
VOPC_Profile P,
PatLeaf cond = COND_NULL,
string revOp = opName,
bit DefExec = 0> {
def _e32 : VOPC_Pseudo <opName, P>,
Commutable_REV<revOp#"_e32", !eq(revOp, opName)> {
let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
let SchedRW = P.Schedule;
let isConvergent = DefExec;
let isCompare = 1;
let isCommutable = 1;
}
def _e64 : VOP3_PseudoNew<opName, P,
!if(P.HasModifiers,
[(set i1:$sdst,
(setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
i1:$clamp, i32:$omod)),
(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
cond))],
[(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))])>,
Commutable_REV<revOp#"_e64", !eq(revOp, opName)> {
let Defs = !if(DefExec, [EXEC], []);
let SchedRW = P.Schedule;
let isCompare = 1;
let isCommutable = 1;
}
}
def VOPC_I1_F32_F32 : VOPC_Profile<[Write32Bit], f32>;
def VOPC_I1_F64_F64 : VOPC_Profile<[WriteDoubleAdd], f64>;
def VOPC_I1_I32_I32 : VOPC_Profile<[Write32Bit], i32>;
def VOPC_I1_I64_I64 : VOPC_Profile<[Write64Bit], i64>;
multiclass VOPC_F32 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
VOPC_Pseudos <opName, VOPC_I1_F32_F32, cond, revOp, 0>;
multiclass VOPC_F64 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
VOPC_Pseudos <opName, VOPC_I1_F64_F64, cond, revOp, 0>;
multiclass VOPC_I32 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
VOPC_Pseudos <opName, VOPC_I1_I32_I32, cond, revOp, 0>;
multiclass VOPC_I64 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
VOPC_Pseudos <opName, VOPC_I1_I64_I64, cond, revOp, 0>;
multiclass VOPCX_F32 <string opName, string revOp = opName> :
VOPC_Pseudos <opName, VOPC_I1_F32_F32, COND_NULL, revOp, 1>;
multiclass VOPCX_F64 <string opName, string revOp = opName> :
VOPC_Pseudos <opName, VOPC_I1_F64_F64, COND_NULL, revOp, 1>;
multiclass VOPCX_I32 <string opName, string revOp = opName> :
VOPC_Pseudos <opName, VOPC_I1_I32_I32, COND_NULL, revOp, 1>;
multiclass VOPCX_I64 <string opName, string revOp = opName> :
VOPC_Pseudos <opName, VOPC_I1_I64_I64, COND_NULL, revOp, 1>;
//===----------------------------------------------------------------------===//
// Compare instructions
//===----------------------------------------------------------------------===//
defm V_CMP_F_F32 : VOPC_F32 <"v_cmp_f_f32">;
defm V_CMP_LT_F32 : VOPC_F32 <"v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">;
defm V_CMP_EQ_F32 : VOPC_F32 <"v_cmp_eq_f32", COND_OEQ>;
defm V_CMP_LE_F32 : VOPC_F32 <"v_cmp_le_f32", COND_OLE, "v_cmp_ge_f32">;
defm V_CMP_GT_F32 : VOPC_F32 <"v_cmp_gt_f32", COND_OGT>;
defm V_CMP_LG_F32 : VOPC_F32 <"v_cmp_lg_f32", COND_ONE>;
defm V_CMP_GE_F32 : VOPC_F32 <"v_cmp_ge_f32", COND_OGE>;
defm V_CMP_O_F32 : VOPC_F32 <"v_cmp_o_f32", COND_O>;
defm V_CMP_U_F32 : VOPC_F32 <"v_cmp_u_f32", COND_UO>;
defm V_CMP_NGE_F32 : VOPC_F32 <"v_cmp_nge_f32", COND_ULT, "v_cmp_nle_f32">;
defm V_CMP_NLG_F32 : VOPC_F32 <"v_cmp_nlg_f32", COND_UEQ>;
defm V_CMP_NGT_F32 : VOPC_F32 <"v_cmp_ngt_f32", COND_ULE, "v_cmp_nlt_f32">;
defm V_CMP_NLE_F32 : VOPC_F32 <"v_cmp_nle_f32", COND_UGT>;
defm V_CMP_NEQ_F32 : VOPC_F32 <"v_cmp_neq_f32", COND_UNE>;
defm V_CMP_NLT_F32 : VOPC_F32 <"v_cmp_nlt_f32", COND_UGE>;
defm V_CMP_TRU_F32 : VOPC_F32 <"v_cmp_tru_f32">;
defm V_CMPX_F_F32 : VOPCX_F32 <"v_cmpx_f_f32">;
defm V_CMPX_LT_F32 : VOPCX_F32 <"v_cmpx_lt_f32", "v_cmpx_gt_f32">;
defm V_CMPX_EQ_F32 : VOPCX_F32 <"v_cmpx_eq_f32">;
defm V_CMPX_LE_F32 : VOPCX_F32 <"v_cmpx_le_f32", "v_cmpx_ge_f32">;
defm V_CMPX_GT_F32 : VOPCX_F32 <"v_cmpx_gt_f32">;
defm V_CMPX_LG_F32 : VOPCX_F32 <"v_cmpx_lg_f32">;
defm V_CMPX_GE_F32 : VOPCX_F32 <"v_cmpx_ge_f32">;
defm V_CMPX_O_F32 : VOPCX_F32 <"v_cmpx_o_f32">;
defm V_CMPX_U_F32 : VOPCX_F32 <"v_cmpx_u_f32">;
defm V_CMPX_NGE_F32 : VOPCX_F32 <"v_cmpx_nge_f32">;
defm V_CMPX_NLG_F32 : VOPCX_F32 <"v_cmpx_nlg_f32">;
defm V_CMPX_NGT_F32 : VOPCX_F32 <"v_cmpx_ngt_f32">;
defm V_CMPX_NLE_F32 : VOPCX_F32 <"v_cmpx_nle_f32">;
defm V_CMPX_NEQ_F32 : VOPCX_F32 <"v_cmpx_neq_f32">;
defm V_CMPX_NLT_F32 : VOPCX_F32 <"v_cmpx_nlt_f32">;
defm V_CMPX_TRU_F32 : VOPCX_F32 <"v_cmpx_tru_f32">;
defm V_CMP_F_F64 : VOPC_F64 <"v_cmp_f_f64">;
defm V_CMP_LT_F64 : VOPC_F64 <"v_cmp_lt_f64", COND_OLT, "v_cmp_gt_f64">;
defm V_CMP_EQ_F64 : VOPC_F64 <"v_cmp_eq_f64", COND_OEQ>;
defm V_CMP_LE_F64 : VOPC_F64 <"v_cmp_le_f64", COND_OLE, "v_cmp_ge_f64">;
defm V_CMP_GT_F64 : VOPC_F64 <"v_cmp_gt_f64", COND_OGT>;
defm V_CMP_LG_F64 : VOPC_F64 <"v_cmp_lg_f64", COND_ONE>;
defm V_CMP_GE_F64 : VOPC_F64 <"v_cmp_ge_f64", COND_OGE>;
defm V_CMP_O_F64 : VOPC_F64 <"v_cmp_o_f64", COND_O>;
defm V_CMP_U_F64 : VOPC_F64 <"v_cmp_u_f64", COND_UO>;
defm V_CMP_NGE_F64 : VOPC_F64 <"v_cmp_nge_f64", COND_ULT, "v_cmp_nle_f64">;
defm V_CMP_NLG_F64 : VOPC_F64 <"v_cmp_nlg_f64", COND_UEQ>;
defm V_CMP_NGT_F64 : VOPC_F64 <"v_cmp_ngt_f64", COND_ULE, "v_cmp_nlt_f64">;
defm V_CMP_NLE_F64 : VOPC_F64 <"v_cmp_nle_f64", COND_UGT>;
defm V_CMP_NEQ_F64 : VOPC_F64 <"v_cmp_neq_f64", COND_UNE>;
defm V_CMP_NLT_F64 : VOPC_F64 <"v_cmp_nlt_f64", COND_UGE>;
defm V_CMP_TRU_F64 : VOPC_F64 <"v_cmp_tru_f64">;
defm V_CMPX_F_F64 : VOPCX_F64 <"v_cmpx_f_f64">;
defm V_CMPX_LT_F64 : VOPCX_F64 <"v_cmpx_lt_f64", "v_cmpx_gt_f64">;
defm V_CMPX_EQ_F64 : VOPCX_F64 <"v_cmpx_eq_f64">;
defm V_CMPX_LE_F64 : VOPCX_F64 <"v_cmpx_le_f64", "v_cmpx_ge_f64">;
defm V_CMPX_GT_F64 : VOPCX_F64 <"v_cmpx_gt_f64">;
defm V_CMPX_LG_F64 : VOPCX_F64 <"v_cmpx_lg_f64">;
defm V_CMPX_GE_F64 : VOPCX_F64 <"v_cmpx_ge_f64">;
defm V_CMPX_O_F64 : VOPCX_F64 <"v_cmpx_o_f64">;
defm V_CMPX_U_F64 : VOPCX_F64 <"v_cmpx_u_f64">;
defm V_CMPX_NGE_F64 : VOPCX_F64 <"v_cmpx_nge_f64", "v_cmpx_nle_f64">;
defm V_CMPX_NLG_F64 : VOPCX_F64 <"v_cmpx_nlg_f64">;
defm V_CMPX_NGT_F64 : VOPCX_F64 <"v_cmpx_ngt_f64", "v_cmpx_nlt_f64">;
defm V_CMPX_NLE_F64 : VOPCX_F64 <"v_cmpx_nle_f64">;
defm V_CMPX_NEQ_F64 : VOPCX_F64 <"v_cmpx_neq_f64">;
defm V_CMPX_NLT_F64 : VOPCX_F64 <"v_cmpx_nlt_f64">;
defm V_CMPX_TRU_F64 : VOPCX_F64 <"v_cmpx_tru_f64">;
let SubtargetPredicate = isSICI in {
defm V_CMPS_F_F32 : VOPC_F32 <"v_cmps_f_f32">;
defm V_CMPS_LT_F32 : VOPC_F32 <"v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">;
defm V_CMPS_EQ_F32 : VOPC_F32 <"v_cmps_eq_f32">;
defm V_CMPS_LE_F32 : VOPC_F32 <"v_cmps_le_f32", COND_NULL, "v_cmps_ge_f32">;
defm V_CMPS_GT_F32 : VOPC_F32 <"v_cmps_gt_f32">;
defm V_CMPS_LG_F32 : VOPC_F32 <"v_cmps_lg_f32">;
defm V_CMPS_GE_F32 : VOPC_F32 <"v_cmps_ge_f32">;
defm V_CMPS_O_F32 : VOPC_F32 <"v_cmps_o_f32">;
defm V_CMPS_U_F32 : VOPC_F32 <"v_cmps_u_f32">;
defm V_CMPS_NGE_F32 : VOPC_F32 <"v_cmps_nge_f32", COND_NULL, "v_cmps_nle_f32">;
defm V_CMPS_NLG_F32 : VOPC_F32 <"v_cmps_nlg_f32">;
defm V_CMPS_NGT_F32 : VOPC_F32 <"v_cmps_ngt_f32", COND_NULL, "v_cmps_nlt_f32">;
defm V_CMPS_NLE_F32 : VOPC_F32 <"v_cmps_nle_f32">;
defm V_CMPS_NEQ_F32 : VOPC_F32 <"v_cmps_neq_f32">;
defm V_CMPS_NLT_F32 : VOPC_F32 <"v_cmps_nlt_f32">;
defm V_CMPS_TRU_F32 : VOPC_F32 <"v_cmps_tru_f32">;
defm V_CMPSX_F_F32 : VOPCX_F32 <"v_cmpsx_f_f32">;
defm V_CMPSX_LT_F32 : VOPCX_F32 <"v_cmpsx_lt_f32", "v_cmpsx_gt_f32">;
defm V_CMPSX_EQ_F32 : VOPCX_F32 <"v_cmpsx_eq_f32">;
defm V_CMPSX_LE_F32 : VOPCX_F32 <"v_cmpsx_le_f32", "v_cmpsx_ge_f32">;
defm V_CMPSX_GT_F32 : VOPCX_F32 <"v_cmpsx_gt_f32">;
defm V_CMPSX_LG_F32 : VOPCX_F32 <"v_cmpsx_lg_f32">;
defm V_CMPSX_GE_F32 : VOPCX_F32 <"v_cmpsx_ge_f32">;
defm V_CMPSX_O_F32 : VOPCX_F32 <"v_cmpsx_o_f32">;
defm V_CMPSX_U_F32 : VOPCX_F32 <"v_cmpsx_u_f32">;
defm V_CMPSX_NGE_F32 : VOPCX_F32 <"v_cmpsx_nge_f32", "v_cmpsx_nle_f32">;
defm V_CMPSX_NLG_F32 : VOPCX_F32 <"v_cmpsx_nlg_f32">;
defm V_CMPSX_NGT_F32 : VOPCX_F32 <"v_cmpsx_ngt_f32", "v_cmpsx_nlt_f32">;
defm V_CMPSX_NLE_F32 : VOPCX_F32 <"v_cmpsx_nle_f32">;
defm V_CMPSX_NEQ_F32 : VOPCX_F32 <"v_cmpsx_neq_f32">;
defm V_CMPSX_NLT_F32 : VOPCX_F32 <"v_cmpsx_nlt_f32">;
defm V_CMPSX_TRU_F32 : VOPCX_F32 <"v_cmpsx_tru_f32">;
defm V_CMPS_F_F64 : VOPC_F64 <"v_cmps_f_f64">;
defm V_CMPS_LT_F64 : VOPC_F64 <"v_cmps_lt_f64", COND_NULL, "v_cmps_gt_f64">;
defm V_CMPS_EQ_F64 : VOPC_F64 <"v_cmps_eq_f64">;
defm V_CMPS_LE_F64 : VOPC_F64 <"v_cmps_le_f64", COND_NULL, "v_cmps_ge_f64">;
defm V_CMPS_GT_F64 : VOPC_F64 <"v_cmps_gt_f64">;
defm V_CMPS_LG_F64 : VOPC_F64 <"v_cmps_lg_f64">;
defm V_CMPS_GE_F64 : VOPC_F64 <"v_cmps_ge_f64">;
defm V_CMPS_O_F64 : VOPC_F64 <"v_cmps_o_f64">;
defm V_CMPS_U_F64 : VOPC_F64 <"v_cmps_u_f64">;
defm V_CMPS_NGE_F64 : VOPC_F64 <"v_cmps_nge_f64", COND_NULL, "v_cmps_nle_f64">;
defm V_CMPS_NLG_F64 : VOPC_F64 <"v_cmps_nlg_f64">;
defm V_CMPS_NGT_F64 : VOPC_F64 <"v_cmps_ngt_f64", COND_NULL, "v_cmps_nlt_f64">;
defm V_CMPS_NLE_F64 : VOPC_F64 <"v_cmps_nle_f64">;
defm V_CMPS_NEQ_F64 : VOPC_F64 <"v_cmps_neq_f64">;
defm V_CMPS_NLT_F64 : VOPC_F64 <"v_cmps_nlt_f64">;
defm V_CMPS_TRU_F64 : VOPC_F64 <"v_cmps_tru_f64">;
defm V_CMPSX_F_F64 : VOPCX_F64 <"v_cmpsx_f_f64">;
defm V_CMPSX_LT_F64 : VOPCX_F64 <"v_cmpsx_lt_f64", "v_cmpsx_gt_f64">;
defm V_CMPSX_EQ_F64 : VOPCX_F64 <"v_cmpsx_eq_f64">;
defm V_CMPSX_LE_F64 : VOPCX_F64 <"v_cmpsx_le_f64", "v_cmpsx_ge_f64">;
defm V_CMPSX_GT_F64 : VOPCX_F64 <"v_cmpsx_gt_f64">;
defm V_CMPSX_LG_F64 : VOPCX_F64 <"v_cmpsx_lg_f64">;
defm V_CMPSX_GE_F64 : VOPCX_F64 <"v_cmpsx_ge_f64">;
defm V_CMPSX_O_F64 : VOPCX_F64 <"v_cmpsx_o_f64">;
defm V_CMPSX_U_F64 : VOPCX_F64 <"v_cmpsx_u_f64">;
defm V_CMPSX_NGE_F64 : VOPCX_F64 <"v_cmpsx_nge_f64", "v_cmpsx_nle_f64">;
defm V_CMPSX_NLG_F64 : VOPCX_F64 <"v_cmpsx_nlg_f64">;
defm V_CMPSX_NGT_F64 : VOPCX_F64 <"v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">;
defm V_CMPSX_NLE_F64 : VOPCX_F64 <"v_cmpsx_nle_f64">;
defm V_CMPSX_NEQ_F64 : VOPCX_F64 <"v_cmpsx_neq_f64">;
defm V_CMPSX_NLT_F64 : VOPCX_F64 <"v_cmpsx_nlt_f64">;
defm V_CMPSX_TRU_F64 : VOPCX_F64 <"v_cmpsx_tru_f64">;
} // End SubtargetPredicate = isSICI
defm V_CMP_F_I32 : VOPC_I32 <"v_cmp_f_i32">;
defm V_CMP_LT_I32 : VOPC_I32 <"v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">;
defm V_CMP_EQ_I32 : VOPC_I32 <"v_cmp_eq_i32", COND_EQ>;
defm V_CMP_LE_I32 : VOPC_I32 <"v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">;
defm V_CMP_GT_I32 : VOPC_I32 <"v_cmp_gt_i32", COND_SGT>;
defm V_CMP_NE_I32 : VOPC_I32 <"v_cmp_ne_i32", COND_NE>;
defm V_CMP_GE_I32 : VOPC_I32 <"v_cmp_ge_i32", COND_SGE>;
defm V_CMP_T_I32 : VOPC_I32 <"v_cmp_t_i32">;
defm V_CMPX_F_I32 : VOPCX_I32 <"v_cmpx_f_i32">;
defm V_CMPX_LT_I32 : VOPCX_I32 <"v_cmpx_lt_i32", "v_cmpx_gt_i32">;
defm V_CMPX_EQ_I32 : VOPCX_I32 <"v_cmpx_eq_i32">;
defm V_CMPX_LE_I32 : VOPCX_I32 <"v_cmpx_le_i32", "v_cmpx_ge_i32">;
defm V_CMPX_GT_I32 : VOPCX_I32 <"v_cmpx_gt_i32">;
defm V_CMPX_NE_I32 : VOPCX_I32 <"v_cmpx_ne_i32">;
defm V_CMPX_GE_I32 : VOPCX_I32 <"v_cmpx_ge_i32">;
defm V_CMPX_T_I32 : VOPCX_I32 <"v_cmpx_t_i32">;
defm V_CMP_F_I64 : VOPC_I64 <"v_cmp_f_i64">;
defm V_CMP_LT_I64 : VOPC_I64 <"v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">;
defm V_CMP_EQ_I64 : VOPC_I64 <"v_cmp_eq_i64", COND_EQ>;
defm V_CMP_LE_I64 : VOPC_I64 <"v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">;
defm V_CMP_GT_I64 : VOPC_I64 <"v_cmp_gt_i64", COND_SGT>;
defm V_CMP_NE_I64 : VOPC_I64 <"v_cmp_ne_i64", COND_NE>;
defm V_CMP_GE_I64 : VOPC_I64 <"v_cmp_ge_i64", COND_SGE>;
defm V_CMP_T_I64 : VOPC_I64 <"v_cmp_t_i64">;
defm V_CMPX_F_I64 : VOPCX_I64 <"v_cmpx_f_i64">;
defm V_CMPX_LT_I64 : VOPCX_I64 <"v_cmpx_lt_i64", "v_cmpx_gt_i64">;
defm V_CMPX_EQ_I64 : VOPCX_I64 <"v_cmpx_eq_i64">;
defm V_CMPX_LE_I64 : VOPCX_I64 <"v_cmpx_le_i64", "v_cmpx_ge_i64">;
defm V_CMPX_GT_I64 : VOPCX_I64 <"v_cmpx_gt_i64">;
defm V_CMPX_NE_I64 : VOPCX_I64 <"v_cmpx_ne_i64">;
defm V_CMPX_GE_I64 : VOPCX_I64 <"v_cmpx_ge_i64">;
defm V_CMPX_T_I64 : VOPCX_I64 <"v_cmpx_t_i64">;
defm V_CMP_F_U32 : VOPC_I32 <"v_cmp_f_u32">;
defm V_CMP_LT_U32 : VOPC_I32 <"v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">;
defm V_CMP_EQ_U32 : VOPC_I32 <"v_cmp_eq_u32", COND_EQ>;
defm V_CMP_LE_U32 : VOPC_I32 <"v_cmp_le_u32", COND_ULE, "v_cmp_ge_u32">;
defm V_CMP_GT_U32 : VOPC_I32 <"v_cmp_gt_u32", COND_UGT>;
defm V_CMP_NE_U32 : VOPC_I32 <"v_cmp_ne_u32", COND_NE>;
defm V_CMP_GE_U32 : VOPC_I32 <"v_cmp_ge_u32", COND_UGE>;
defm V_CMP_T_U32 : VOPC_I32 <"v_cmp_t_u32">;
defm V_CMPX_F_U32 : VOPCX_I32 <"v_cmpx_f_u32">;
defm V_CMPX_LT_U32 : VOPCX_I32 <"v_cmpx_lt_u32", "v_cmpx_gt_u32">;
defm V_CMPX_EQ_U32 : VOPCX_I32 <"v_cmpx_eq_u32">;
defm V_CMPX_LE_U32 : VOPCX_I32 <"v_cmpx_le_u32", "v_cmpx_le_u32">;
defm V_CMPX_GT_U32 : VOPCX_I32 <"v_cmpx_gt_u32">;
defm V_CMPX_NE_U32 : VOPCX_I32 <"v_cmpx_ne_u32">;
defm V_CMPX_GE_U32 : VOPCX_I32 <"v_cmpx_ge_u32">;
defm V_CMPX_T_U32 : VOPCX_I32 <"v_cmpx_t_u32">;
defm V_CMP_F_U64 : VOPC_I64 <"v_cmp_f_u64">;
defm V_CMP_LT_U64 : VOPC_I64 <"v_cmp_lt_u64", COND_ULT, "v_cmp_gt_u64">;
defm V_CMP_EQ_U64 : VOPC_I64 <"v_cmp_eq_u64", COND_EQ>;
defm V_CMP_LE_U64 : VOPC_I64 <"v_cmp_le_u64", COND_ULE, "v_cmp_ge_u64">;
defm V_CMP_GT_U64 : VOPC_I64 <"v_cmp_gt_u64", COND_UGT>;
defm V_CMP_NE_U64 : VOPC_I64 <"v_cmp_ne_u64", COND_NE>;
defm V_CMP_GE_U64 : VOPC_I64 <"v_cmp_ge_u64", COND_UGE>;
defm V_CMP_T_U64 : VOPC_I64 <"v_cmp_t_u64">;
defm V_CMPX_F_U64 : VOPCX_I64 <"v_cmpx_f_u64">;
defm V_CMPX_LT_U64 : VOPCX_I64 <"v_cmpx_lt_u64", "v_cmpx_gt_u64">;
defm V_CMPX_EQ_U64 : VOPCX_I64 <"v_cmpx_eq_u64">;
defm V_CMPX_LE_U64 : VOPCX_I64 <"v_cmpx_le_u64", "v_cmpx_ge_u64">;
defm V_CMPX_GT_U64 : VOPCX_I64 <"v_cmpx_gt_u64">;
defm V_CMPX_NE_U64 : VOPCX_I64 <"v_cmpx_ne_u64">;
defm V_CMPX_GE_U64 : VOPCX_I64 <"v_cmpx_ge_u64">;
defm V_CMPX_T_U64 : VOPCX_I64 <"v_cmpx_t_u64">;
//===----------------------------------------------------------------------===//
// Class instructions
//===----------------------------------------------------------------------===//
class VOPC_Class_Profile<list<SchedReadWrite> sched, ValueType vt> :
VOPC_Profile<sched, vt, i32> {
let Ins64 = (ins Src0Mod:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
let Asm64 = "$sdst, $src0_modifiers, $src1";
let InsSDWA = (ins Src0Mod:$src0_fmodifiers, Src0RC64:$src0,
Int32InputMods:$src1_imodifiers, Src1RC64:$src1,
clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel);
let AsmSDWA = " vcc, $src0_fmodifiers, $src1_imodifiers$clamp $src0_sel $src1_sel";
let HasClamp = 0;
let HasOMod = 0;
}
class getVOPCClassPat64 <VOPProfile P> {
list<dag> ret =
[(set i1:$sdst,
(AMDGPUfp_class
(P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)),
P.Src1VT:$src1))];
}
// Special case for class instructions which only have modifiers on
// the 1st source operand.
multiclass VOPC_Class_Pseudos <string opName, VOPC_Profile p, bit DefExec> {
def _e32 : VOPC_Pseudo <opName, p> {
let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
let SchedRW = p.Schedule;
let isConvergent = DefExec;
}
def _e64 : VOP3_PseudoNew<opName, p, getVOPCClassPat64<p>.ret> {
let Defs = !if(DefExec, [EXEC], []);
let SchedRW = p.Schedule;
}
}
def VOPC_I1_F32_I32 : VOPC_Class_Profile<[Write32Bit], f32>;
def VOPC_I1_F64_I32 : VOPC_Class_Profile<[WriteDoubleAdd], f64>;
multiclass VOPC_CLASS_F32 <string opName> :
VOPC_Class_Pseudos <opName, VOPC_I1_F32_I32, 0>;
multiclass VOPCX_CLASS_F32 <string opName> :
VOPC_Class_Pseudos <opName, VOPC_I1_F32_I32, 1>;
multiclass VOPC_CLASS_F64 <string opName> :
VOPC_Class_Pseudos <opName, VOPC_I1_F64_I32, 0>;
multiclass VOPCX_CLASS_F64 <string opName> :
VOPC_Class_Pseudos <opName, VOPC_I1_F64_I32, 1>;
defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <"v_cmp_class_f32">;
defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <"v_cmpx_class_f32">;
defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <"v_cmp_class_f64">;
defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <"v_cmpx_class_f64">;
//===----------------------------------------------------------------------===//
// V_ICMPIntrinsic Pattern.
//===----------------------------------------------------------------------===//
let Predicates = [isGCN] in {
class ICMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> : Pat <
(AMDGPUsetcc vt:$src0, vt:$src1, cond),
(inst $src0, $src1)
>;
def : ICMP_Pattern <COND_EQ, V_CMP_EQ_I32_e64, i32>;
def : ICMP_Pattern <COND_NE, V_CMP_NE_I32_e64, i32>;
def : ICMP_Pattern <COND_UGT, V_CMP_GT_U32_e64, i32>;
def : ICMP_Pattern <COND_UGE, V_CMP_GE_U32_e64, i32>;
def : ICMP_Pattern <COND_ULT, V_CMP_LT_U32_e64, i32>;
def : ICMP_Pattern <COND_ULE, V_CMP_LE_U32_e64, i32>;
def : ICMP_Pattern <COND_SGT, V_CMP_GT_I32_e64, i32>;
def : ICMP_Pattern <COND_SGE, V_CMP_GE_I32_e64, i32>;
def : ICMP_Pattern <COND_SLT, V_CMP_LT_I32_e64, i32>;
def : ICMP_Pattern <COND_SLE, V_CMP_LE_I32_e64, i32>;
def : ICMP_Pattern <COND_EQ, V_CMP_EQ_I64_e64, i64>;
def : ICMP_Pattern <COND_NE, V_CMP_NE_I64_e64, i64>;
def : ICMP_Pattern <COND_UGT, V_CMP_GT_U64_e64, i64>;
def : ICMP_Pattern <COND_UGE, V_CMP_GE_U64_e64, i64>;
def : ICMP_Pattern <COND_ULT, V_CMP_LT_U64_e64, i64>;
def : ICMP_Pattern <COND_ULE, V_CMP_LE_U64_e64, i64>;
def : ICMP_Pattern <COND_SGT, V_CMP_GT_I64_e64, i64>;
def : ICMP_Pattern <COND_SGE, V_CMP_GE_I64_e64, i64>;
def : ICMP_Pattern <COND_SLT, V_CMP_LT_I64_e64, i64>;
def : ICMP_Pattern <COND_SLE, V_CMP_LE_I64_e64, i64>;
class FCMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> : Pat <
(i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
(vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),
(inst $src0_modifiers, $src0, $src1_modifiers, $src1,
DSTCLAMP.NONE, DSTOMOD.NONE)
>;
def : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F32_e64, f32>;
def : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F32_e64, f32>;
def : FCMP_Pattern <COND_OGT, V_CMP_GT_F32_e64, f32>;
def : FCMP_Pattern <COND_OGE, V_CMP_GE_F32_e64, f32>;
def : FCMP_Pattern <COND_OLT, V_CMP_LT_F32_e64, f32>;
def : FCMP_Pattern <COND_OLE, V_CMP_LE_F32_e64, f32>;
def : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F64_e64, f64>;
def : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F64_e64, f64>;
def : FCMP_Pattern <COND_OGT, V_CMP_GT_F64_e64, f64>;
def : FCMP_Pattern <COND_OGE, V_CMP_GE_F64_e64, f64>;
def : FCMP_Pattern <COND_OLT, V_CMP_LT_F64_e64, f64>;
def : FCMP_Pattern <COND_OLE, V_CMP_LE_F64_e64, f64>;
def : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F32_e64, f32>;
def : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F32_e64, f32>;
def : FCMP_Pattern <COND_UGT, V_CMP_NLE_F32_e64, f32>;
def : FCMP_Pattern <COND_UGE, V_CMP_NLT_F32_e64, f32>;
def : FCMP_Pattern <COND_ULT, V_CMP_NGE_F32_e64, f32>;
def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F32_e64, f32>;
def : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F64_e64, f64>;
def : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F64_e64, f64>;
def : FCMP_Pattern <COND_UGT, V_CMP_NLE_F64_e64, f64>;
def : FCMP_Pattern <COND_UGE, V_CMP_NLT_F64_e64, f64>;
def : FCMP_Pattern <COND_ULT, V_CMP_NGE_F64_e64, f64>;
def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F64_e64, f64>;
} // End Predicates = [isGCN]
//===----------------------------------------------------------------------===//
// Target
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// SI
//===----------------------------------------------------------------------===//
multiclass VOPC_Real_si <bits<9> op> {
let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in {
def _e32_si :
VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
VOPCe<op{7-0}>;
def _e64_si :
VOP3_Real<!cast<VOP3_PseudoNew>(NAME#"_e64"), SIEncodingFamily.SI>,
VOP3a_siNew <op, !cast<VOP3_PseudoNew>(NAME#"_e64").Pfl> {
// Encoding used for VOPC instructions encoded as VOP3
// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
bits<8> sdst;
let Inst{7-0} = sdst;
}
}
def : VOPCInstAlias <!cast<VOP3_PseudoNew>(NAME#"_e64"),
!cast<Instruction>(NAME#"_e32_si")> {
let AssemblerPredicate = isSICI;
}
}
defm V_CMP_F_F32 : VOPC_Real_si <0x0>;
defm V_CMP_LT_F32 : VOPC_Real_si <0x1>;
defm V_CMP_EQ_F32 : VOPC_Real_si <0x2>;
defm V_CMP_LE_F32 : VOPC_Real_si <0x3>;
defm V_CMP_GT_F32 : VOPC_Real_si <0x4>;
defm V_CMP_LG_F32 : VOPC_Real_si <0x5>;
defm V_CMP_GE_F32 : VOPC_Real_si <0x6>;
defm V_CMP_O_F32 : VOPC_Real_si <0x7>;
defm V_CMP_U_F32 : VOPC_Real_si <0x8>;
defm V_CMP_NGE_F32 : VOPC_Real_si <0x9>;
defm V_CMP_NLG_F32 : VOPC_Real_si <0xa>;
defm V_CMP_NGT_F32 : VOPC_Real_si <0xb>;
defm V_CMP_NLE_F32 : VOPC_Real_si <0xc>;
defm V_CMP_NEQ_F32 : VOPC_Real_si <0xd>;
defm V_CMP_NLT_F32 : VOPC_Real_si <0xe>;
defm V_CMP_TRU_F32 : VOPC_Real_si <0xf>;
defm V_CMPX_F_F32 : VOPC_Real_si <0x10>;
defm V_CMPX_LT_F32 : VOPC_Real_si <0x11>;
defm V_CMPX_EQ_F32 : VOPC_Real_si <0x12>;
defm V_CMPX_LE_F32 : VOPC_Real_si <0x13>;
defm V_CMPX_GT_F32 : VOPC_Real_si <0x14>;
defm V_CMPX_LG_F32 : VOPC_Real_si <0x15>;
defm V_CMPX_GE_F32 : VOPC_Real_si <0x16>;
defm V_CMPX_O_F32 : VOPC_Real_si <0x17>;
defm V_CMPX_U_F32 : VOPC_Real_si <0x18>;
defm V_CMPX_NGE_F32 : VOPC_Real_si <0x19>;
defm V_CMPX_NLG_F32 : VOPC_Real_si <0x1a>;
defm V_CMPX_NGT_F32 : VOPC_Real_si <0x1b>;
defm V_CMPX_NLE_F32 : VOPC_Real_si <0x1c>;
defm V_CMPX_NEQ_F32 : VOPC_Real_si <0x1d>;
defm V_CMPX_NLT_F32 : VOPC_Real_si <0x1e>;
defm V_CMPX_TRU_F32 : VOPC_Real_si <0x1f>;
defm V_CMP_F_F64 : VOPC_Real_si <0x20>;
defm V_CMP_LT_F64 : VOPC_Real_si <0x21>;
defm V_CMP_EQ_F64 : VOPC_Real_si <0x22>;
defm V_CMP_LE_F64 : VOPC_Real_si <0x23>;
defm V_CMP_GT_F64 : VOPC_Real_si <0x24>;
defm V_CMP_LG_F64 : VOPC_Real_si <0x25>;
defm V_CMP_GE_F64 : VOPC_Real_si <0x26>;
defm V_CMP_O_F64 : VOPC_Real_si <0x27>;
defm V_CMP_U_F64 : VOPC_Real_si <0x28>;
defm V_CMP_NGE_F64 : VOPC_Real_si <0x29>;
defm V_CMP_NLG_F64 : VOPC_Real_si <0x2a>;
defm V_CMP_NGT_F64 : VOPC_Real_si <0x2b>;
defm V_CMP_NLE_F64 : VOPC_Real_si <0x2c>;
defm V_CMP_NEQ_F64 : VOPC_Real_si <0x2d>;
defm V_CMP_NLT_F64 : VOPC_Real_si <0x2e>;
defm V_CMP_TRU_F64 : VOPC_Real_si <0x2f>;
defm V_CMPX_F_F64 : VOPC_Real_si <0x30>;
defm V_CMPX_LT_F64 : VOPC_Real_si <0x31>;
defm V_CMPX_EQ_F64 : VOPC_Real_si <0x32>;
defm V_CMPX_LE_F64 : VOPC_Real_si <0x33>;
defm V_CMPX_GT_F64 : VOPC_Real_si <0x34>;
defm V_CMPX_LG_F64 : VOPC_Real_si <0x35>;
defm V_CMPX_GE_F64 : VOPC_Real_si <0x36>;
defm V_CMPX_O_F64 : VOPC_Real_si <0x37>;
defm V_CMPX_U_F64 : VOPC_Real_si <0x38>;
defm V_CMPX_NGE_F64 : VOPC_Real_si <0x39>;
defm V_CMPX_NLG_F64 : VOPC_Real_si <0x3a>;
defm V_CMPX_NGT_F64 : VOPC_Real_si <0x3b>;
defm V_CMPX_NLE_F64 : VOPC_Real_si <0x3c>;
defm V_CMPX_NEQ_F64 : VOPC_Real_si <0x3d>;
defm V_CMPX_NLT_F64 : VOPC_Real_si <0x3e>;
defm V_CMPX_TRU_F64 : VOPC_Real_si <0x3f>;
defm V_CMPS_F_F32 : VOPC_Real_si <0x40>;
defm V_CMPS_LT_F32 : VOPC_Real_si <0x41>;
defm V_CMPS_EQ_F32 : VOPC_Real_si <0x42>;
defm V_CMPS_LE_F32 : VOPC_Real_si <0x43>;
defm V_CMPS_GT_F32 : VOPC_Real_si <0x44>;
defm V_CMPS_LG_F32 : VOPC_Real_si <0x45>;
defm V_CMPS_GE_F32 : VOPC_Real_si <0x46>;
defm V_CMPS_O_F32 : VOPC_Real_si <0x47>;
defm V_CMPS_U_F32 : VOPC_Real_si <0x48>;
defm V_CMPS_NGE_F32 : VOPC_Real_si <0x49>;
defm V_CMPS_NLG_F32 : VOPC_Real_si <0x4a>;
defm V_CMPS_NGT_F32 : VOPC_Real_si <0x4b>;
defm V_CMPS_NLE_F32 : VOPC_Real_si <0x4c>;
defm V_CMPS_NEQ_F32 : VOPC_Real_si <0x4d>;
defm V_CMPS_NLT_F32 : VOPC_Real_si <0x4e>;
defm V_CMPS_TRU_F32 : VOPC_Real_si <0x4f>;
defm V_CMPSX_F_F32 : VOPC_Real_si <0x50>;
defm V_CMPSX_LT_F32 : VOPC_Real_si <0x51>;
defm V_CMPSX_EQ_F32 : VOPC_Real_si <0x52>;
defm V_CMPSX_LE_F32 : VOPC_Real_si <0x53>;
defm V_CMPSX_GT_F32 : VOPC_Real_si <0x54>;
defm V_CMPSX_LG_F32 : VOPC_Real_si <0x55>;
defm V_CMPSX_GE_F32 : VOPC_Real_si <0x56>;
defm V_CMPSX_O_F32 : VOPC_Real_si <0x57>;
defm V_CMPSX_U_F32 : VOPC_Real_si <0x58>;
defm V_CMPSX_NGE_F32 : VOPC_Real_si <0x59>;
defm V_CMPSX_NLG_F32 : VOPC_Real_si <0x5a>;
defm V_CMPSX_NGT_F32 : VOPC_Real_si <0x5b>;
defm V_CMPSX_NLE_F32 : VOPC_Real_si <0x5c>;
defm V_CMPSX_NEQ_F32 : VOPC_Real_si <0x5d>;
defm V_CMPSX_NLT_F32 : VOPC_Real_si <0x5e>;
defm V_CMPSX_TRU_F32 : VOPC_Real_si <0x5f>;
defm V_CMPS_F_F64 : VOPC_Real_si <0x60>;
defm V_CMPS_LT_F64 : VOPC_Real_si <0x61>;
defm V_CMPS_EQ_F64 : VOPC_Real_si <0x62>;
defm V_CMPS_LE_F64 : VOPC_Real_si <0x63>;
defm V_CMPS_GT_F64 : VOPC_Real_si <0x64>;
defm V_CMPS_LG_F64 : VOPC_Real_si <0x65>;
defm V_CMPS_GE_F64 : VOPC_Real_si <0x66>;
defm V_CMPS_O_F64 : VOPC_Real_si <0x67>;
defm V_CMPS_U_F64 : VOPC_Real_si <0x68>;
defm V_CMPS_NGE_F64 : VOPC_Real_si <0x69>;
defm V_CMPS_NLG_F64 : VOPC_Real_si <0x6a>;
defm V_CMPS_NGT_F64 : VOPC_Real_si <0x6b>;
defm V_CMPS_NLE_F64 : VOPC_Real_si <0x6c>;
defm V_CMPS_NEQ_F64 : VOPC_Real_si <0x6d>;
defm V_CMPS_NLT_F64 : VOPC_Real_si <0x6e>;
defm V_CMPS_TRU_F64 : VOPC_Real_si <0x6f>;
defm V_CMPSX_F_F64 : VOPC_Real_si <0x70>;
defm V_CMPSX_LT_F64 : VOPC_Real_si <0x71>;
defm V_CMPSX_EQ_F64 : VOPC_Real_si <0x72>;
defm V_CMPSX_LE_F64 : VOPC_Real_si <0x73>;
defm V_CMPSX_GT_F64 : VOPC_Real_si <0x74>;
defm V_CMPSX_LG_F64 : VOPC_Real_si <0x75>;
defm V_CMPSX_GE_F64 : VOPC_Real_si <0x76>;
defm V_CMPSX_O_F64 : VOPC_Real_si <0x77>;
defm V_CMPSX_U_F64 : VOPC_Real_si <0x78>;
defm V_CMPSX_NGE_F64 : VOPC_Real_si <0x79>;
defm V_CMPSX_NLG_F64 : VOPC_Real_si <0x7a>;
defm V_CMPSX_NGT_F64 : VOPC_Real_si <0x7b>;
defm V_CMPSX_NLE_F64 : VOPC_Real_si <0x7c>;
defm V_CMPSX_NEQ_F64 : VOPC_Real_si <0x7d>;
defm V_CMPSX_NLT_F64 : VOPC_Real_si <0x7e>;
defm V_CMPSX_TRU_F64 : VOPC_Real_si <0x7f>;
defm V_CMP_F_I32 : VOPC_Real_si <0x80>;
defm V_CMP_LT_I32 : VOPC_Real_si <0x81>;
defm V_CMP_EQ_I32 : VOPC_Real_si <0x82>;
defm V_CMP_LE_I32 : VOPC_Real_si <0x83>;
defm V_CMP_GT_I32 : VOPC_Real_si <0x84>;
defm V_CMP_NE_I32 : VOPC_Real_si <0x85>;
defm V_CMP_GE_I32 : VOPC_Real_si <0x86>;
defm V_CMP_T_I32 : VOPC_Real_si <0x87>;
defm V_CMPX_F_I32 : VOPC_Real_si <0x90>;
defm V_CMPX_LT_I32 : VOPC_Real_si <0x91>;
defm V_CMPX_EQ_I32 : VOPC_Real_si <0x92>;
defm V_CMPX_LE_I32 : VOPC_Real_si <0x93>;
defm V_CMPX_GT_I32 : VOPC_Real_si <0x94>;
defm V_CMPX_NE_I32 : VOPC_Real_si <0x95>;
defm V_CMPX_GE_I32 : VOPC_Real_si <0x96>;
defm V_CMPX_T_I32 : VOPC_Real_si <0x97>;
defm V_CMP_F_I64 : VOPC_Real_si <0xa0>;
defm V_CMP_LT_I64 : VOPC_Real_si <0xa1>;
defm V_CMP_EQ_I64 : VOPC_Real_si <0xa2>;
defm V_CMP_LE_I64 : VOPC_Real_si <0xa3>;
defm V_CMP_GT_I64 : VOPC_Real_si <0xa4>;
defm V_CMP_NE_I64 : VOPC_Real_si <0xa5>;
defm V_CMP_GE_I64 : VOPC_Real_si <0xa6>;
defm V_CMP_T_I64 : VOPC_Real_si <0xa7>;
defm V_CMPX_F_I64 : VOPC_Real_si <0xb0>;
defm V_CMPX_LT_I64 : VOPC_Real_si <0xb1>;
defm V_CMPX_EQ_I64 : VOPC_Real_si <0xb2>;
defm V_CMPX_LE_I64 : VOPC_Real_si <0xb3>;
defm V_CMPX_GT_I64 : VOPC_Real_si <0xb4>;
defm V_CMPX_NE_I64 : VOPC_Real_si <0xb5>;
defm V_CMPX_GE_I64 : VOPC_Real_si <0xb6>;
defm V_CMPX_T_I64 : VOPC_Real_si <0xb7>;
defm V_CMP_F_U32 : VOPC_Real_si <0xc0>;
defm V_CMP_LT_U32 : VOPC_Real_si <0xc1>;
defm V_CMP_EQ_U32 : VOPC_Real_si <0xc2>;
defm V_CMP_LE_U32 : VOPC_Real_si <0xc3>;
defm V_CMP_GT_U32 : VOPC_Real_si <0xc4>;
defm V_CMP_NE_U32 : VOPC_Real_si <0xc5>;
defm V_CMP_GE_U32 : VOPC_Real_si <0xc6>;
defm V_CMP_T_U32 : VOPC_Real_si <0xc7>;
defm V_CMPX_F_U32 : VOPC_Real_si <0xd0>;
defm V_CMPX_LT_U32 : VOPC_Real_si <0xd1>;
defm V_CMPX_EQ_U32 : VOPC_Real_si <0xd2>;
defm V_CMPX_LE_U32 : VOPC_Real_si <0xd3>;
defm V_CMPX_GT_U32 : VOPC_Real_si <0xd4>;
defm V_CMPX_NE_U32 : VOPC_Real_si <0xd5>;
defm V_CMPX_GE_U32 : VOPC_Real_si <0xd6>;
defm V_CMPX_T_U32 : VOPC_Real_si <0xd7>;
defm V_CMP_F_U64 : VOPC_Real_si <0xe0>;
defm V_CMP_LT_U64 : VOPC_Real_si <0xe1>;
defm V_CMP_EQ_U64 : VOPC_Real_si <0xe2>;
defm V_CMP_LE_U64 : VOPC_Real_si <0xe3>;
defm V_CMP_GT_U64 : VOPC_Real_si <0xe4>;
defm V_CMP_NE_U64 : VOPC_Real_si <0xe5>;
defm V_CMP_GE_U64 : VOPC_Real_si <0xe6>;
defm V_CMP_T_U64 : VOPC_Real_si <0xe7>;
defm V_CMPX_F_U64 : VOPC_Real_si <0xf0>;
defm V_CMPX_LT_U64 : VOPC_Real_si <0xf1>;
defm V_CMPX_EQ_U64 : VOPC_Real_si <0xf2>;
defm V_CMPX_LE_U64 : VOPC_Real_si <0xf3>;
defm V_CMPX_GT_U64 : VOPC_Real_si <0xf4>;
defm V_CMPX_NE_U64 : VOPC_Real_si <0xf5>;
defm V_CMPX_GE_U64 : VOPC_Real_si <0xf6>;
defm V_CMPX_T_U64 : VOPC_Real_si <0xf7>;
defm V_CMP_CLASS_F32 : VOPC_Real_si <0x88>;
defm V_CMPX_CLASS_F32 : VOPC_Real_si <0x98>;
defm V_CMP_CLASS_F64 : VOPC_Real_si <0xa8>;
defm V_CMPX_CLASS_F64 : VOPC_Real_si <0xb8>;
//===----------------------------------------------------------------------===//
// VI
//===----------------------------------------------------------------------===//
class VOPC_SDWAe <bits<8> op, VOPProfile P> : VOP_SDWAeNew<P> {
bits<8> src1;
let Inst{8-0} = 0xf9; // sdwa
let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
let Inst{24-17} = op;
let Inst{31-25} = 0x3e; // encoding
// VOPC disallows dst_sel and dst_unused as they have no effect on destination
let Inst{42-40} = SDWA_DWORD;
let Inst{44-43} = SDWA_UNUSED_PRESERVE;
}
class VOPC_SDWA<bits<8> op, VOPC_Pseudo ps, VOPProfile p = ps.Pfl> :
VOP_SDWA <p.OutsSDWA, p.InsSDWA, ps.OpName#p.AsmSDWA, [], p.HasModifiers>,
VOPC_SDWAe <op, p> {
let Defs = ps.Defs;
let hasSideEffects = ps.hasSideEffects;
let AsmMatchConverter = "cvtSdwaVOPC";
let SubtargetPredicate = isVI;
let AssemblerPredicate = !if(p.HasExt, isVI, DisableInst);
let AsmVariantName = !if(p.HasExt, AMDGPUAsmVariants.SDWA,
AMDGPUAsmVariants.Disable);
let DecoderNamespace = "SDWA";
let isCompare = ps.isCompare;
let isCommutable = ps.isCommutable;
}
multiclass VOPC_Real_vi <bits<10> op> {
let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
def _e32_vi :
VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
VOPCe<op{7-0}>;
def _e64_vi :
VOP3_Real<!cast<VOP3_PseudoNew>(NAME#"_e64"), SIEncodingFamily.VI>,
VOP3a_viNew <op, !cast<VOP3_PseudoNew>(NAME#"_e64").Pfl> {
// Encoding used for VOPC instructions encoded as VOP3
// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
bits<8> sdst;
let Inst{7-0} = sdst;
}
}
// for now left sdwa only for asm/dasm
// TODO: add corresponding pseudo
def _sdwa : VOPC_SDWA<op{7-0}, !cast<VOPC_Pseudo>(NAME#"_e32")>;
def : VOPCInstAlias <!cast<VOP3_PseudoNew>(NAME#"_e64"),
!cast<Instruction>(NAME#"_e32_vi")> {
let AssemblerPredicate = isVI;
}
}
defm V_CMP_F_F32 : VOPC_Real_vi <0x40>;
defm V_CMP_LT_F32 : VOPC_Real_vi <0x41>;
defm V_CMP_EQ_F32 : VOPC_Real_vi <0x42>;
defm V_CMP_LE_F32 : VOPC_Real_vi <0x43>;
defm V_CMP_GT_F32 : VOPC_Real_vi <0x44>;
defm V_CMP_LG_F32 : VOPC_Real_vi <0x45>;
defm V_CMP_GE_F32 : VOPC_Real_vi <0x46>;
defm V_CMP_O_F32 : VOPC_Real_vi <0x47>;
defm V_CMP_U_F32 : VOPC_Real_vi <0x48>;
defm V_CMP_NGE_F32 : VOPC_Real_vi <0x49>;
defm V_CMP_NLG_F32 : VOPC_Real_vi <0x4a>;
defm V_CMP_NGT_F32 : VOPC_Real_vi <0x4b>;
defm V_CMP_NLE_F32 : VOPC_Real_vi <0x4c>;
defm V_CMP_NEQ_F32 : VOPC_Real_vi <0x4d>;
defm V_CMP_NLT_F32 : VOPC_Real_vi <0x4e>;
defm V_CMP_TRU_F32 : VOPC_Real_vi <0x4f>;
defm V_CMPX_F_F32 : VOPC_Real_vi <0x50>;
defm V_CMPX_LT_F32 : VOPC_Real_vi <0x51>;
defm V_CMPX_EQ_F32 : VOPC_Real_vi <0x52>;
defm V_CMPX_LE_F32 : VOPC_Real_vi <0x53>;
defm V_CMPX_GT_F32 : VOPC_Real_vi <0x54>;
defm V_CMPX_LG_F32 : VOPC_Real_vi <0x55>;
defm V_CMPX_GE_F32 : VOPC_Real_vi <0x56>;
defm V_CMPX_O_F32 : VOPC_Real_vi <0x57>;
defm V_CMPX_U_F32 : VOPC_Real_vi <0x58>;
defm V_CMPX_NGE_F32 : VOPC_Real_vi <0x59>;
defm V_CMPX_NLG_F32 : VOPC_Real_vi <0x5a>;
defm V_CMPX_NGT_F32 : VOPC_Real_vi <0x5b>;
defm V_CMPX_NLE_F32 : VOPC_Real_vi <0x5c>;
defm V_CMPX_NEQ_F32 : VOPC_Real_vi <0x5d>;
defm V_CMPX_NLT_F32 : VOPC_Real_vi <0x5e>;
defm V_CMPX_TRU_F32 : VOPC_Real_vi <0x5f>;
defm V_CMP_F_F64 : VOPC_Real_vi <0x60>;
defm V_CMP_LT_F64 : VOPC_Real_vi <0x61>;
defm V_CMP_EQ_F64 : VOPC_Real_vi <0x62>;
defm V_CMP_LE_F64 : VOPC_Real_vi <0x63>;
defm V_CMP_GT_F64 : VOPC_Real_vi <0x64>;
defm V_CMP_LG_F64 : VOPC_Real_vi <0x65>;
defm V_CMP_GE_F64 : VOPC_Real_vi <0x66>;
defm V_CMP_O_F64 : VOPC_Real_vi <0x67>;
defm V_CMP_U_F64 : VOPC_Real_vi <0x68>;
defm V_CMP_NGE_F64 : VOPC_Real_vi <0x69>;
defm V_CMP_NLG_F64 : VOPC_Real_vi <0x6a>;
defm V_CMP_NGT_F64 : VOPC_Real_vi <0x6b>;
defm V_CMP_NLE_F64 : VOPC_Real_vi <0x6c>;
defm V_CMP_NEQ_F64 : VOPC_Real_vi <0x6d>;
defm V_CMP_NLT_F64 : VOPC_Real_vi <0x6e>;
defm V_CMP_TRU_F64 : VOPC_Real_vi <0x6f>;
defm V_CMPX_F_F64 : VOPC_Real_vi <0x70>;
defm V_CMPX_LT_F64 : VOPC_Real_vi <0x71>;
defm V_CMPX_EQ_F64 : VOPC_Real_vi <0x72>;
defm V_CMPX_LE_F64 : VOPC_Real_vi <0x73>;
defm V_CMPX_GT_F64 : VOPC_Real_vi <0x74>;
defm V_CMPX_LG_F64 : VOPC_Real_vi <0x75>;
defm V_CMPX_GE_F64 : VOPC_Real_vi <0x76>;
defm V_CMPX_O_F64 : VOPC_Real_vi <0x77>;
defm V_CMPX_U_F64 : VOPC_Real_vi <0x78>;
defm V_CMPX_NGE_F64 : VOPC_Real_vi <0x79>;
defm V_CMPX_NLG_F64 : VOPC_Real_vi <0x7a>;
defm V_CMPX_NGT_F64 : VOPC_Real_vi <0x7b>;
defm V_CMPX_NLE_F64 : VOPC_Real_vi <0x7c>;
defm V_CMPX_NEQ_F64 : VOPC_Real_vi <0x7d>;
defm V_CMPX_NLT_F64 : VOPC_Real_vi <0x7e>;
defm V_CMPX_TRU_F64 : VOPC_Real_vi <0x7f>;
defm V_CMP_F_I32 : VOPC_Real_vi <0xc0>;
defm V_CMP_LT_I32 : VOPC_Real_vi <0xc1>;
defm V_CMP_EQ_I32 : VOPC_Real_vi <0xc2>;
defm V_CMP_LE_I32 : VOPC_Real_vi <0xc3>;
defm V_CMP_GT_I32 : VOPC_Real_vi <0xc4>;
defm V_CMP_NE_I32 : VOPC_Real_vi <0xc5>;
defm V_CMP_GE_I32 : VOPC_Real_vi <0xc6>;
defm V_CMP_T_I32 : VOPC_Real_vi <0xc7>;
defm V_CMPX_F_I32 : VOPC_Real_vi <0xd0>;
defm V_CMPX_LT_I32 : VOPC_Real_vi <0xd1>;
defm V_CMPX_EQ_I32 : VOPC_Real_vi <0xd2>;
defm V_CMPX_LE_I32 : VOPC_Real_vi <0xd3>;
defm V_CMPX_GT_I32 : VOPC_Real_vi <0xd4>;
defm V_CMPX_NE_I32 : VOPC_Real_vi <0xd5>;
defm V_CMPX_GE_I32 : VOPC_Real_vi <0xd6>;
defm V_CMPX_T_I32 : VOPC_Real_vi <0xd7>;
defm V_CMP_F_I64 : VOPC_Real_vi <0xe0>;
defm V_CMP_LT_I64 : VOPC_Real_vi <0xe1>;
defm V_CMP_EQ_I64 : VOPC_Real_vi <0xe2>;
defm V_CMP_LE_I64 : VOPC_Real_vi <0xe3>;
defm V_CMP_GT_I64 : VOPC_Real_vi <0xe4>;
defm V_CMP_NE_I64 : VOPC_Real_vi <0xe5>;
defm V_CMP_GE_I64 : VOPC_Real_vi <0xe6>;
defm V_CMP_T_I64 : VOPC_Real_vi <0xe7>;
defm V_CMPX_F_I64 : VOPC_Real_vi <0xf0>;
defm V_CMPX_LT_I64 : VOPC_Real_vi <0xf1>;
defm V_CMPX_EQ_I64 : VOPC_Real_vi <0xf2>;
defm V_CMPX_LE_I64 : VOPC_Real_vi <0xf3>;
defm V_CMPX_GT_I64 : VOPC_Real_vi <0xf4>;
defm V_CMPX_NE_I64 : VOPC_Real_vi <0xf5>;
defm V_CMPX_GE_I64 : VOPC_Real_vi <0xf6>;
defm V_CMPX_T_I64 : VOPC_Real_vi <0xf7>;
defm V_CMP_F_U32 : VOPC_Real_vi <0xc8>;
defm V_CMP_LT_U32 : VOPC_Real_vi <0xc9>;
defm V_CMP_EQ_U32 : VOPC_Real_vi <0xca>;
defm V_CMP_LE_U32 : VOPC_Real_vi <0xcb>;
defm V_CMP_GT_U32 : VOPC_Real_vi <0xcc>;
defm V_CMP_NE_U32 : VOPC_Real_vi <0xcd>;
defm V_CMP_GE_U32 : VOPC_Real_vi <0xce>;
defm V_CMP_T_U32 : VOPC_Real_vi <0xcf>;
defm V_CMPX_F_U32 : VOPC_Real_vi <0xd8>;
defm V_CMPX_LT_U32 : VOPC_Real_vi <0xd9>;
defm V_CMPX_EQ_U32 : VOPC_Real_vi <0xda>;
defm V_CMPX_LE_U32 : VOPC_Real_vi <0xdb>;
defm V_CMPX_GT_U32 : VOPC_Real_vi <0xdc>;
defm V_CMPX_NE_U32 : VOPC_Real_vi <0xdd>;
defm V_CMPX_GE_U32 : VOPC_Real_vi <0xde>;
defm V_CMPX_T_U32 : VOPC_Real_vi <0xdf>;
defm V_CMP_F_U64 : VOPC_Real_vi <0xe8>;
defm V_CMP_LT_U64 : VOPC_Real_vi <0xe9>;
defm V_CMP_EQ_U64 : VOPC_Real_vi <0xea>;
defm V_CMP_LE_U64 : VOPC_Real_vi <0xeb>;
defm V_CMP_GT_U64 : VOPC_Real_vi <0xec>;
defm V_CMP_NE_U64 : VOPC_Real_vi <0xed>;
defm V_CMP_GE_U64 : VOPC_Real_vi <0xee>;
defm V_CMP_T_U64 : VOPC_Real_vi <0xef>;
defm V_CMPX_F_U64 : VOPC_Real_vi <0xf8>;
defm V_CMPX_LT_U64 : VOPC_Real_vi <0xf9>;
defm V_CMPX_EQ_U64 : VOPC_Real_vi <0xfa>;
defm V_CMPX_LE_U64 : VOPC_Real_vi <0xfb>;
defm V_CMPX_GT_U64 : VOPC_Real_vi <0xfc>;
defm V_CMPX_NE_U64 : VOPC_Real_vi <0xfd>;
defm V_CMPX_GE_U64 : VOPC_Real_vi <0xfe>;
defm V_CMPX_T_U64 : VOPC_Real_vi <0xff>;
defm V_CMP_CLASS_F32 : VOPC_Real_vi <0x10>;
defm V_CMPX_CLASS_F32 : VOPC_Real_vi <0x11>;
defm V_CMP_CLASS_F64 : VOPC_Real_vi <0x12>;
defm V_CMPX_CLASS_F64 : VOPC_Real_vi <0x13>;

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//===-- VOPInstructions.td - Vector Instruction Defintions ----------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
class VOP3_PseudoNew <string opName, VOPProfile P, list<dag> pattern, bit VOP3Only = 0> :
InstSI <P.Outs64, P.Ins64, "", pattern>,
VOP <opName>,
SIMCInstr<opName#"_e64", SIEncodingFamily.NONE>,
MnemonicAlias<opName#"_e64", opName> {
let isPseudo = 1;
let isCodeGenOnly = 1;
let UseNamedOperandTable = 1;
string Mnemonic = opName;
string AsmOperands = P.Asm64;
let Size = 8;
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let SubtargetPredicate = isGCN;
// Because SGPRs may be allowed if there are multiple operands, we
// need a post-isel hook to insert copies in order to avoid
// violating constant bus requirements.
let hasPostISelHook = 1;
// Using complex patterns gives VOP3 patterns a very high complexity rating,
// but standalone patterns are almost always prefered, so we need to adjust the
// priority lower. The goal is to use a high number to reduce complexity to
// zero (or less than zero).
let AddedComplexity = -1000;
let VOP3 = 1;
let VALU = 1;
let Uses = [EXEC];
let AsmVariantName = AMDGPUAsmVariants.VOP3;
let AsmMatchConverter =
!if(!eq(VOP3Only,1),
"cvtVOP3",
!if(!eq(P.HasModifiers, 1), "cvtVOP3_2_mod", ""));
VOPProfile Pfl = P;
}
class VOP3_Real <VOP3_PseudoNew ps, int EncodingFamily> :
InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
SIMCInstr <ps.PseudoInstr, EncodingFamily> {
let isPseudo = 0;
let isCodeGenOnly = 0;
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
let AsmVariantName = ps.AsmVariantName;
let Constraints = ps.Constraints;
let DisableEncoding = ps.DisableEncoding;
let TSFlags = ps.TSFlags;
}
class VOP3aNew<VOPProfile P> : Enc64 {
bits<2> src0_modifiers;
bits<9> src0;
bits<2> src1_modifiers;
bits<9> src1;
bits<2> src2_modifiers;
bits<9> src2;
bits<1> clamp;
bits<2> omod;
let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0);
let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0);
let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0);
let Inst{31-26} = 0x34; //encoding
let Inst{40-32} = src0;
let Inst{49-41} = !if(P.HasSrc1, src1, 0);
let Inst{58-50} = !if(P.HasSrc2, src2, 0);
let Inst{60-59} = !if(P.HasOMod, omod, 0);
let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0);
let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0);
let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0);
}
class VOP3a_siNew <bits<9> op, VOPProfile P> : VOP3aNew<P> {
let Inst{25-17} = op;
let Inst{11} = !if(P.HasClamp, clamp, 0);
}
class VOP3a_viNew <bits<10> op, VOPProfile P> : VOP3aNew<P> {
let Inst{25-16} = op;
let Inst{15} = !if(P.HasClamp, clamp, 0);
}
class VOP_SDWAeNew<VOPProfile P> : Enc64 {
bits<8> src0;
bits<3> src0_sel;
bits<2> src0_fmodifiers; // {abs,neg}
bits<1> src0_imodifiers; // sext
bits<3> src1_sel;
bits<2> src1_fmodifiers;
bits<1> src1_imodifiers;
bits<3> dst_sel;
bits<2> dst_unused;
bits<1> clamp;
bits<3> SDWA_DWORD = 6;
bits<2> SDWA_UNUSED_PRESERVE = 2;
let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
let Inst{42-40} = !if(P.HasDst, dst_sel{2-0}, SDWA_DWORD{2-0});
let Inst{44-43} = !if(P.HasDst, dst_unused{1-0}, SDWA_UNUSED_PRESERVE{1-0});
let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0);
let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, SDWA_DWORD{2-0});
let Inst{53-52} = !if(P.HasSrc0Mods, src0_fmodifiers{1-0}, 0);
let Inst{51} = !if(P.HasSrc0IntMods, src0_imodifiers{0}, 0);
let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, SDWA_DWORD{2-0});
let Inst{61-60} = !if(P.HasSrc1Mods, src1_fmodifiers{1-0}, 0);
let Inst{59} = !if(P.HasSrc1IntMods, src1_imodifiers{0}, 0);
}
include "VOPCInstructions.td"