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[PPC] Add intrinsics for vector extract word and vector insert word.

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Revision: https://reviews.llvm.org/D26547

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289227 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sean Fertile 2016-12-09 17:21:42 +00:00
parent 2c96583422
commit d22c85d068
3 changed files with 34 additions and 0 deletions
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7
include/llvm/IR/IntrinsicsPowerPC.td
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@ -889,6 +889,13 @@ def int_ppc_vsx_xvtstdcsp :
def int_ppc_vsx_xvcvhpsp :
PowerPC_VSX_Intrinsic<"xvcvhpsp", [llvm_v4f32_ty],
[llvm_v8i16_ty],[IntrNoMem]>;
def int_ppc_vsx_xxextractuw :
PowerPC_VSX_Intrinsic<"xxextractuw",[llvm_v2i64_ty],
[llvm_v2i64_ty,llvm_i32_ty], [IntrNoMem]>;
def int_ppc_vsx_xxinsertw :
PowerPC_VSX_Intrinsic<"xxinsertw",[llvm_v4i32_ty],
[llvm_v4i32_ty,llvm_v2i64_ty,llvm_i32_ty],
[IntrNoMem]>;
}
//===----------------------------------------------------------------------===//

9
lib/Target/PowerPC/PPCInstrVSX.td
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@ -2262,6 +2262,14 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
[(set v4i32: $XT,
(int_ppc_vsx_xvxsigsp v4f32:$XB))]>;
let AddedComplexity = 400, Predicates = [HasP9Vector] in {
// Extra patterns expanding to vector Extract Word/Insert Word
def : Pat<(v4i32 (int_ppc_vsx_xxinsertw v4i32:$A, v2i64:$B, imm:$IMM)),
(v4i32 (XXINSERTW $A, $B, imm:$IMM))>;
def : Pat<(v2i64 (int_ppc_vsx_xxextractuw v2i64:$A, imm:$IMM)),
(v2i64 (COPY_TO_REGCLASS (XXEXTRACTUW $A, imm:$IMM), VSRC))>;
} // AddedComplexity = 400, HasP9Vector
//===--------------------------------------------------------------------===//
// Test Data Class SP/DP/QP
@ -2632,6 +2640,7 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
(STXSIHXv (VSLDOI $S, $S, 10), xoaddr:$dst)>;
} // IsLittleEndian, HasP9Vector
// Vector sign extensions
def : Pat<(f64 (PPCVexts f64:$A, 1)),
(f64 (COPY_TO_REGCLASS (VEXTSB2Ds $A), VSFRC))>;

18
test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll
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@ -990,3 +990,21 @@ entry:
%vecins = insertelement <4 x i32> %a, i32 %i, i32 %el
ret <4 x i32> %vecins
}
define <4 x i32> @intrinsicInsertTest(<4 x i32> %a, <2 x i64> %b) {
entry:
; CHECK-LABEL:intrinsicInsertTest
; CHECK: xxinsertw 34, 35, 3
; CHECK: blr
%ans = tail call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> %a, <2 x i64> %b, i32 3)
ret <4 x i32> %ans
}
declare <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32>, <2 x i64>, i32)
define <2 x i64> @intrinsicExtractTest(<2 x i64> %a) {
entry:
; CHECK-LABEL: intrinsicExtractTest
; CHECK: xxextractuw 0, 34, 5
; CHECK: blr
%ans = tail call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> %a, i32 5)
ret <2 x i64> %ans
}
declare <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64>, i32)