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TargetSchedule: Allow explicit Unsupported markers in InstRW

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262549 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun 2016-03-03 00:05:07 +00:00
parent 0101cb0a0b
commit d29de67f2b
1 changed files with 2 additions and 0 deletions
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include/llvm/Target/TargetSchedule.td
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@ -393,6 +393,8 @@ class InstRW<list<SchedReadWrite> rw, dag instrlist> {
list<SchedReadWrite> OperandReadWrites = rw; list<SchedReadWrite> OperandReadWrites = rw;
dag Instrs = instrlist; dag Instrs = instrlist;
SchedMachineModel SchedModel = ?; SchedMachineModel SchedModel = ?;
// Allow a subtarget to mark some instructions as unsupported.
bit Unsupported = 0;
} }
// Map a set of itinerary classes to SchedReadWrite resources. This is // Map a set of itinerary classes to SchedReadWrite resources. This is