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[X86] Add knownbits vector SUB test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286508 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -203,3 +203,26 @@ define <4 x i32> @knownbits_mask_trunc_shuffle_shl(<4 x i64> %a0) nounwind {
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%4 = shl <4 x i32> %3, <i32 22, i32 22, i32 22, i32 22>
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ret <4 x i32> %4
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}
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define <4 x i32> @knownbits_sub_lshr(<4 x i32> %a0) nounwind {
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; X32-LABEL: knownbits_sub_lshr:
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; X32: # BB#0:
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; X32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0
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; X32-NEXT: vmovdqa {{.*#+}} xmm1 = [255,255,255,255]
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; X32-NEXT: vpsubd %xmm0, %xmm1, %xmm0
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; X32-NEXT: vpsrld $22, %xmm0, %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: knownbits_sub_lshr:
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; X64: # BB#0:
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; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
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; X64-NEXT: vmovdqa {{.*#+}} xmm1 = [255,255,255,255]
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; X64-NEXT: vpsubd %xmm0, %xmm1, %xmm0
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; X64-NEXT: vpsrld $22, %xmm0, %xmm0
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; X64-NEXT: retq
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%1 = and <4 x i32> %a0, <i32 15, i32 15, i32 15, i32 15>
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%2 = sub <4 x i32> <i32 255, i32 255, i32 255, i32 255>, %1
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%3 = lshr <4 x i32> %2, <i32 22, i32 22, i32 22, i32 22>
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ret <4 x i32> %3
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}
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