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AMDGPU: mark atomic instructions as sources of divergence
Summary: As explained by the comment, threads will typically see different values returned by atomic instructions even if the arguments are equal. Reviewers: arsenm, tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18156 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263719 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -186,6 +186,13 @@ bool AMDGPUTTIImpl::isSourceOfDivergence(const Value *V) const {
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if (const LoadInst *Load = dyn_cast<LoadInst>(V))
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return Load->getPointerAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
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// Atomics are divergent because they are executed sequentially: when an
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// atomic operation refers to the same address in each thread, then each
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// thread after the first sees the value written by the previous thread as
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// original value.
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if (isa<AtomicRMWInst>(V) || isa<AtomicCmpXchgInst>(V))
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return true;
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if (const IntrinsicInst *Intrinsic = dyn_cast<IntrinsicInst>(V)) {
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const TargetMachine &TM = getTLI()->getTargetMachine();
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return isIntrinsicSourceOfDivergence(TM.getIntrinsicInfo(), Intrinsic);
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15
test/Analysis/DivergenceAnalysis/AMDGPU/atomics.ll
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15
test/Analysis/DivergenceAnalysis/AMDGPU/atomics.ll
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@ -0,0 +1,15 @@
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; RUN: opt -mtriple=amdgcn-- -analyze -divergence %s | FileCheck %s
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; CHECK: DIVERGENT: %orig = atomicrmw xchg i32* %ptr, i32 %val seq_cst
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define i32 @test1(i32* %ptr, i32 %val) #0 {
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%orig = atomicrmw xchg i32* %ptr, i32 %val seq_cst
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ret i32 %orig
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}
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; CHECK: DIVERGENT: %orig = cmpxchg i32* %ptr, i32 %cmp, i32 %new seq_cst seq_cst
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define {i32, i1} @test2(i32* %ptr, i32 %cmp, i32 %new) {
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%orig = cmpxchg i32* %ptr, i32 %cmp, i32 %new seq_cst seq_cst
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ret {i32, i1} %orig
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}
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attributes #0 = { "ShaderType"="0" }
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