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[AArch64] AArch64LoadStoreOptimizer: fix bug in pre-inc check iterator

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Summary:
Fix case where a pre-inc/dec load/store would not be formed if the
add/sub that forms the inc/dec part of the operation was the first
instruction in the block being examined.

Reviewers: mcrosier, jmolloy, t.p.northover, junbuml

Subscribers: aemerson, rengolin, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D16785

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260275 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Geoff Berry 2016-02-09 20:47:21 +00:00
parent a9adb28214
commit d3a670dcad
2 changed files with 11 additions and 10 deletions
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17
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
View File

@ -1023,6 +1023,8 @@ static void trackRegDefsUses(const MachineInstr *MI, BitVector &ModifiedRegs,
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
if (!Reg)
continue;
if (MO.isDef()) {
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
ModifiedRegs.set(*AI);
@ -1496,15 +1498,14 @@ MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward(
// (inclusive) and the second insn.
ModifiedRegs.reset();
UsedRegs.reset();
--MBBI;
for (unsigned Count = 0; MBBI != B && Count < Limit; --MBBI) {
unsigned Count = 0;
do {
--MBBI;
MachineInstr *MI = MBBI;
// Skip DBG_VALUE instructions.
if (MI->isDebugValue())
continue;
// Now that we know this is a real instruction, count it.
++Count;
// Don't count DBG_VALUE instructions towards the search limit.
if (!MI->isDebugValue())
++Count;
// If we found a match, return it.
if (isMatchingUpdateInsn(I, MI, BaseReg, Offset))
@ -1517,7 +1518,7 @@ MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward(
// return early.
if (ModifiedRegs[BaseReg] || UsedRegs[BaseReg])
return E;
}
} while (MBBI != B && Count < Limit);
return E;
}

4
test/CodeGen/AArch64/arm64-nvcast.ll
View File

@ -2,7 +2,7 @@
; CHECK-LABEL: _test:
; CHECK: fmov.2d v0, #2.00000000
; CHECK: str q0, [sp]
; CHECK: str q0, [sp, #-16]!
; CHECK: mov x8, sp
; CHECK: ldr s0, [x8, w1, sxtw #2]
; CHECK: str s0, [x0]
@ -16,7 +16,7 @@ entry:
; CHECK-LABEL: _test2
; CHECK: movi.16b v0, #0x3f
; CHECK: str q0, [sp]
; CHECK: str q0, [sp, #-16]!
; CHECK: mov x8, sp
; CHECK: ldr s0, [x8, w1, sxtw #2]
; CHECK: str s0, [x0]