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Add iterator_range<regclass_iterator> to {Target,MC}RegisterInfo, NFC

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293077 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek 2017-01-25 19:29:04 +00:00
parent 1a40f3b238
commit d40c764784
8 changed files with 23 additions and 34 deletions
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3
include/llvm/MC/MCRegisterInfo.h
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@ -418,6 +418,9 @@ public:
regclass_iterator regclass_begin() const { return Classes; }
regclass_iterator regclass_end() const { return Classes+NumClasses; }
iterator_range<regclass_iterator> regclasses() const {
return make_range(regclass_begin(), regclass_end());
}
unsigned getNumRegClasses() const {
return (unsigned)(regclass_end()-regclass_begin());

3
include/llvm/Target/TargetRegisterInfo.h
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@ -633,6 +633,9 @@ public:
///
regclass_iterator regclass_begin() const { return RegClassBegin; }
regclass_iterator regclass_end() const { return RegClassEnd; }
iterator_range<regclass_iterator> regclasses() const {
return make_range(regclass_begin(), regclass_end());
}
unsigned getNumRegClasses() const {
return (unsigned)(regclass_end()-regclass_begin());

9
lib/CodeGen/RegisterClassInfo.cpp
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@ -156,9 +156,8 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
const TargetRegisterClass *RC = nullptr;
unsigned NumRCUnits = 0;
for (TargetRegisterInfo::regclass_iterator
RI = TRI->regclass_begin(), RE = TRI->regclass_end(); RI != RE; ++RI) {
const int *PSetID = TRI->getRegClassPressureSets(*RI);
for (const TargetRegisterClass *C : TRI->regclasses()) {
const int *PSetID = TRI->getRegClassPressureSets(C);
for (; *PSetID != -1; ++PSetID) {
if ((unsigned)*PSetID == Idx)
break;
@ -168,9 +167,9 @@ unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
// Found a register class that counts against this pressure set.
// For efficiency, only compute the set order for the largest set.
unsigned NUnits = TRI->getRegClassWeight(*RI).WeightLimit;
unsigned NUnits = TRI->getRegClassWeight(C).WeightLimit;
if (!RC || NUnits > NumRCUnits) {
RC = *RI;
RC = C;
NumRCUnits = NUnits;
}
}

15
lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
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@ -57,10 +57,8 @@ ResourcePriorityQueue::ResourcePriorityQueue(SelectionDAGISel *IS)
RegPressure.resize(NumRC);
std::fill(RegLimit.begin(), RegLimit.end(), 0);
std::fill(RegPressure.begin(), RegPressure.end(), 0);
for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
E = TRI->regclass_end();
I != E; ++I)
RegLimit[(*I)->getID()] = TRI->getRegPressureLimit(*I, *IS->MF);
for (const TargetRegisterClass *RC : TRI->regclasses())
RegLimit[RC->getID()] = TRI->getRegPressureLimit(RC, *IS->MF);
ParallelLiveRanges = 0;
HorizontalVerticalBalance = 0;
@ -364,16 +362,11 @@ int ResourcePriorityQueue::regPressureDelta(SUnit *SU, bool RawPressure) {
return RegBalance;
if (RawPressure) {
for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
E = TRI->regclass_end(); I != E; ++I) {
const TargetRegisterClass *RC = *I;
for (const TargetRegisterClass *RC : TRI->regclasses())
RegBalance += rawRegPressureDelta(SU, RC->getID());
}
}
else {
for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
E = TRI->regclass_end(); I != E; ++I) {
const TargetRegisterClass *RC = *I;
for (const TargetRegisterClass *RC : TRI->regclasses()) {
if ((RegPressure[RC->getID()] +
rawRegPressureDelta(SU, RC->getID()) > 0) &&
(RegPressure[RC->getID()] +

9
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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@ -1659,9 +1659,8 @@ public:
RegPressure.resize(NumRC);
std::fill(RegLimit.begin(), RegLimit.end(), 0);
std::fill(RegPressure.begin(), RegPressure.end(), 0);
for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
E = TRI->regclass_end(); I != E; ++I)
RegLimit[(*I)->getID()] = tri->getRegPressureLimit(*I, MF);
for (const TargetRegisterClass *RC : TRI->regclasses())
RegLimit[RC->getID()] = tri->getRegPressureLimit(RC, MF);
}
}
@ -1926,9 +1925,7 @@ unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const {
void RegReductionPQBase::dumpRegPressure() const {
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
E = TRI->regclass_end(); I != E; ++I) {
const TargetRegisterClass *RC = *I;
for (const TargetRegisterClass *RC : TRI->regclasses()) {
unsigned Id = RC->getID();
unsigned RP = RegPressure[Id];
if (!RP) continue;

5
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -2470,10 +2470,7 @@ TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI,
std::make_pair(0u, static_cast<const TargetRegisterClass*>(nullptr));
// Figure out which register class contains this reg.
for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
E = RI->regclass_end(); RCI != E; ++RCI) {
const TargetRegisterClass *RC = *RCI;
for (const TargetRegisterClass *RC : RI->regclasses()) {
// If none of the value types for this register class are valid, we
// can't use it. For example, 64-bit reg classes on 32-bit targets.
if (!isLegalRC(RC))

10
lib/CodeGen/TargetRegisterInfo.cpp
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@ -155,8 +155,7 @@ TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, MVT VT) const {
// Pick the most sub register class of the right type that contains
// this physreg.
const TargetRegisterClass* BestRC = nullptr;
for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
const TargetRegisterClass* RC = *I;
for (const TargetRegisterClass* RC : regclasses()) {
if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
(!BestRC || BestRC->hasSubClass(RC)))
BestRC = RC;
@ -185,10 +184,9 @@ BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
if (SubClass)
getAllocatableSetForRC(MF, SubClass, Allocatable);
} else {
for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
E = regclass_end(); I != E; ++I)
if ((*I)->isAllocatable())
getAllocatableSetForRC(MF, *I, Allocatable);
for (const TargetRegisterClass *C : regclasses())
if (C->isAllocatable())
getAllocatableSetForRC(MF, C, Allocatable);
}
// Mask out the reserved registers

3
lib/Target/Hexagon/HexagonBlockRanges.cpp
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@ -219,8 +219,7 @@ HexagonBlockRanges::HexagonBlockRanges(MachineFunction &mf)
TII(*HST.getInstrInfo()), TRI(*HST.getRegisterInfo()),
Reserved(TRI.getReservedRegs(mf)) {
// Consider all non-allocatable registers as reserved.
for (auto I = TRI.regclass_begin(), E = TRI.regclass_end(); I != E; ++I) {
auto *RC = *I;
for (const TargetRegisterClass *RC : TRI.regclasses()) {
if (RC->isAllocatable())
continue;
for (unsigned R : *RC)