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[DAG] Fix an assertion failure caused by an invalid cast in method 'BuildVectorSDNode::isConstantSplat'

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This patch renames method 'isConstantSplat' as 'getConstantSplatValue'
(mainly for consistency reasons), and rewrites its logic to ensure
that we always perform a legal 'cast<ConstantSDNode>'.

Added test shift-combine-crash.ll to verify that DAGCombiner no longer crashes with an assertion failure in the attempt to simplify a vector shift by a vector of all undef counts.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204536 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrea Di Biagio 2014-03-22 01:47:22 +00:00
parent 4696def45d
commit d47cb57ab8
4 changed files with 69 additions and 12 deletions
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9
include/llvm/CodeGen/SelectionDAGNodes.h
View File

@ -1522,10 +1522,11 @@ public:
unsigned MinSplatBits = 0, unsigned MinSplatBits = 0,
bool isBigEndian = false) const; bool isBigEndian = false) const;
/// isConstantSplat - Simpler form of isConstantSplat. Get the constant splat /// getConstantSplatValue - Check if this is a constant splat, and if so,
/// when you only care about the value. Returns nullptr if this isn't a /// return the splat value only if it is a ConstantSDNode. Otherwise
/// constant splat vector. /// return nullptr. This is a simpler form of isConstantSplat.
ConstantSDNode *isConstantSplat() const; /// Get the constant splat only if you care about the splat value.
ConstantSDNode *getConstantSplatValue() const;
bool isConstant() const; bool isConstant() const;

2
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -667,7 +667,7 @@ static ConstantSDNode *isConstOrConstSplat(SDValue N) {
return CN; return CN;
if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N))
return BV->isConstantSplat(); return BV->getConstantSplatValue();
return nullptr; return nullptr;
} }

13
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -6573,15 +6573,14 @@ bool BuildVectorSDNode::isConstantSplat(APInt &SplatValue,
return true; return true;
} }
ConstantSDNode *BuildVectorSDNode::isConstantSplat() const { ConstantSDNode *BuildVectorSDNode::getConstantSplatValue() const {
SDValue Op0 = getOperand(0); SDValue Op0 = getOperand(0);
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { if (Op0.getOpcode() != ISD::Constant)
SDValue Opi = getOperand(i); return nullptr;
unsigned Opc = Opi.getOpcode();
if ((Opc != ISD::UNDEF && Opc != ISD::Constant && Opc != ISD::ConstantFP) || for (unsigned i = 1, e = getNumOperands(); i != e; ++i)
Opi != Op0) if (getOperand(i) != Op0)
return nullptr; return nullptr;
}
return cast<ConstantSDNode>(Op0); return cast<ConstantSDNode>(Op0);
} }

57
test/CodeGen/X86/shift-combine-crash.ll Normal file
View File

@ -0,0 +1,57 @@
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 > /dev/null
; Verify that DAGCombiner doesn't crash with an assertion failure in the
; attempt to cast a ISD::UNDEF node to a ConstantSDNode.
; During type legalization, the vector shift operation in function @test1 is
; split into two legal shifts that work on <2 x i64> elements.
; The first shift of the legalized sequence would be a shift by all undefs.
; DAGCombiner will then try to simplify the vector shift and check if the
; vector of shift counts is a splat. Make sure that llc doesn't crash
; at that stage.
define <4 x i64> @test1(<4 x i64> %A) {
%shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 1, i64 2>
ret <4 x i64> %shl
}
; Also, verify that DAGCombiner doesn't crash when trying to combine shifts
; with different combinations of undef elements in the vector shift count.
define <4 x i64> @test2(<4 x i64> %A) {
%shl = shl <4 x i64> %A, <i64 2, i64 3, i64 undef, i64 undef>
ret <4 x i64> %shl
}
define <4 x i64> @test3(<4 x i64> %A) {
%shl = shl <4 x i64> %A, <i64 2, i64 undef, i64 3, i64 undef>
ret <4 x i64> %shl
}
define <4 x i64> @test4(<4 x i64> %A) {
%shl = shl <4 x i64> %A, <i64 undef, i64 2, i64 undef, i64 3>
ret <4 x i64> %shl
}
define <4 x i64> @test5(<4 x i64> %A) {
%shl = shl <4 x i64> %A, <i64 2, i64 undef, i64 undef, i64 undef>
ret <4 x i64> %shl
}
define <4 x i64> @test6(<4 x i64> %A) {
%shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 3, i64 undef>
ret <4 x i64> %shl
}
define <4 x i64> @test7(<4 x i64> %A) {
%shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 undef, i64 3>
ret <4 x i64> %shl
}
define <4 x i64> @test8(<4 x i64> %A) {
%shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 undef, i64 undef>
ret <4 x i64> %shl
}